Gate Oxide Reliability and VTH Stability of Planar SiC MOS Technology

Martin Domeij; Jimmy Franchi; Sotirios Maslougkas; Peter Moens; Jan Lettens; Jake Choi; Fredrik Allerstam

doi:10.4028/p-95van7

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HomeMaterials Science ForumMaterials Science Forum Vol. 1062Gate Oxide Reliability and VTH Stability of Planar...

Gate Oxide Reliability and V_TH Stability of Planar SiC MOS Technology

Abstract:

Similar charge to failure distributions with mean values of about 50 C/cm² were measured for planar SiC MOSFETs and MOS capacitors. Fast occurring and saturating negative flatband and threshold voltage drops were found in time resolved 1 second long pulsed gate current stress with I_G=1 mA/cm² at T=150 °C. No substantial difference in V_TH drift rate with V_GS=28 V at T=150 °C was found after about 10 s recovery period for I_G stressed devices compared with unstressed devices. Additionally, I_G stressed and unstressed devices did not differ in final V_TH shift at T=25 °C after V_GS=28 V stress (during 3 hrs or 31 hrs). More gate oxide reliability characterization is important to determine if 1 mA/cm² pulsed gate current stress creates any permanent changes to the SiC MOSFET device behaviour. Additionally, parametric shifts in V_TH and R_DSon was examined after long-term AC gate bias stress by a gate driver switching between-8V and 20V for four different commercially available SiC MOSFETs.

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Periodical:

Materials Science Forum (Volume 1062)

Pages:

498-503

DOI:

https://doi.org/10.4028/p-95van7

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Online since:

May 2022

Authors:

Martin Domeij*, Jimmy Franchi, Sotirios Maslougkas, Peter Moens, Jan Lettens, Jake Choi, Fredrik Allerstam

Keywords:

Charge to Failure, Gate Bias Stress, MOSFET, Oxide Reliability, Oxide Traps

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Creative Commons CC BY 4.0

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* - Corresponding Author

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