SiC MOSFET C-V Characteristics with Positive Biased Drain

Abstract:

Even if SiC MOSFETs technology has undergone huge progress in last years, there are some issues still open, such as high traps density at the SiO₂/SiC interface. This work focuses on the measurement of the Gate capacitance when a DC bias is applied between Drain and Source to characterize the SiO₂/SiC interface. The experimental curves, performed on a commercial SiC power MOSFET, exhibit a peak when the Gate voltage approaches the threshold voltage. Such peak is analyzed through TCAD simulations and its origin is addressed. Numerical analysis shows that this peak is associated to the displacement current, with a strong dependence on the traps concentration at the SiO₂/SiC interface.

• Periodical: Materials Science Forum (Volume 1062)
• Pages: 653-657
• DOI: https://doi.org/10.4028/p-2tyqfr
• Online since: May 2022
• Authors: Ilaria Matacena*, Luca Maresca, Michele Riccio, Andrea Irace, Giovanni Breglio, Santolo Daliento, Alberto Castellazzi
• Keywords: C-V Curves, Interface Characterization, MOSFET Gate Capacitance, SiC MOSFET, TCAD Model

References

[1] B. J. Baliga, Fundamentals of power semiconductor devices, Springer Science & Business Media, (2010).

[2] C. Raynaud, et al., Comparison of trapping–detrapping properties of mobile charge in alkali contaminated meta,l‐oxide‐silicon carbide structures, Applied physics letters 66, no. 18: 2340-2342, (1995).

DOI: 10.1063/1.113976

[3] S. Daliento, et al. Experimental study on power consumption in lifetime engineered power diodes., IEEE transactions on electron devices 56.11 (2009): 2819-2824.

DOI: 10.1109/ted.2009.2031005

[4] F. Di Napoli, et al. On-line junction temperature monitoring of switching devices with dynamic compact thermal models extracted with model order reduction., Energies 10.2 (2017): 189.

DOI: 10.3390/en10020189

[5] V. V. Afanasev, et al., Intrinsic SiC/SiO2 interface states, physica status solidi (a) 162, no. 1: 321-337, (1997).

DOI: 10.1002/1521-396x(199707)162:1<321::aid-pssa321>3.0.co;2-f

[6] D.Peters et al., Investigation of threshold voltage stability of SiC MOSFETs, ISPSD, (2018).

[7] Dev, Synopsys. Simulation, TCAD Sentaurus Manual.

[8] L. Maresca, et al., Influence of the SiC/SiO2 SiC MOSFET interface traps distribution on CV measurements evaluated by TCAD simulations. IEEE Journal of Emerging and Selected Topics in Power Electronics, (2019).

DOI: 10.1109/jestpe.2019.2940143

[9] G. Romano, et al., A comprehensive study of short-circuit ruggedness of silicon carbide power MOSFETs, IEEE Journal of Emerging and Selected Topics in Power Electronics 4, no. 3 (2016): 978-987.

DOI: 10.1109/jestpe.2016.2563220

[10] Maresca, L., et al., TCAD model calibration for the SiC/SiO2 interface trap in the same of a planar SiC MOSFET. In 2020 IEEE Workshop on Wide Bandgap Power Devices and Applications in Asia (WiPDA Asia) (pp.1-5). IEEE. (2020, September).

DOI: 10.1109/wipdaasia49671.2020.9360298

[11] Matacena, I., et al., Evaluation of Interface Traps Type, Energy Level and Density of SiC MOSFETs by Means of CV Curves TCAD Simulations. In Materials Science Forum (Vol. 1004, pp.608-613). Trans Tech Publications Ltd. (2020).

DOI: 10.4028/www.scientific.net/msf.1004.608