Gate Oxide Performance and Reliability on SmartSiC™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

Tom Becker; Mathias Rommel; Holger Schlichting; Leander Baier; Eric Guiot; Frédéric Allibert

doi:10.4028/p-nh88kE

Paper Titles

Indium-Tin-Oxide (ITO) Interlayer-Assisted Ohmic Contacts on n-Type 4H-SiC with Low Specific Contact Resistance
p.15

Trench Etch Processing for SiC Superjunction Schottky Diodes
p.21

Argon Plasma Treatment of 4H-SiC Surface before Nickel Ohmic Contacts Formation by UV Laser Annealing
p.31

Analysis of Ohmic Contacts Simultaneously Formed on both n-Type and p-Type 4H-SiC
p.37

Gate Oxide Performance and Reliability on SmartSiC™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime
p.45

Damage Evaluation and Elemental Analysis of SiC Wafers Processed by Water Jet Guided Laser
p.55

Formation of Structured Low-Ohmic p-Type Contacts on Al-Implanted 4H-SiC by Laser Annealing
p.61

Fabrication of the Planar SiC Gate-all-Around JFET with Channel Dose Modulation
p.67

Investigation of Poly-Si Gated, Al₂O₃-Based High-k Dielectrics on 4H-SiC
p.73

HomeMaterials Science ForumMaterials Science Forum Vol. 1159Gate Oxide Performance and Reliability on...

Gate Oxide Performance and Reliability on SmartSiC™ Wafers and the Influence of RTA Processing on Gate Oxide Lifetime

Abstract:

In this work, a comparison of standard bulk 4H-SiC epi wafers and Soitec's SmartSiC™ wafers as well as the influence of RTA processing was conducted. For this, MOS capacitors were processed using thermal gate oxide paired with a polycrystalline gate electrode. Subsequent High temperature steps were avoided until an RTA process was performed on some of these wafers. To investigate the oxide quality on all wafer and process splits, CV-, time-zero dielectric breakdown and constant-current stress time-dependent dielectric breakdown measurements were carried out. For the examination of bulk wafers and SmartSiC™, no relevant differences in terms of yield, oxide quality, interface state density and reliability were found. In contrast, RTA processes seem to create a shift in flat band voltage and also lead to a reduction in oxide lifetime. The V_FB shift could partially, but not completely, be explained by addition activation of dopants in the polysilicon electrode. The influence on the oxide reliability, however, is still unclear.

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Periodical:

Materials Science Forum (Volume 1159)

Pages:

45-53

DOI:

https://doi.org/10.4028/p-nh88kE

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Online since:

September 2025

Authors:

Tom Becker*, Mathias Rommel, Holger Schlichting, Leander Baier, Eric Guiot, Frédéric Allibert

Keywords:

Annealing, Gate Oxide, MOS, QBD, Reliability, RTA, Silicon Carbide (SiC), SmartSiC™, TDDB

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Creative Commons CC BY 4.0

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