Influence of Buffer Layer on DC and RF Performance of 4H SiC MESFET

A.V. Los; Michael S. Mazzola; D. Kajfez; B.T. McDaniel; C.E. Smith; James W. Kretchmer; L.B. Rowland; Jeff B. Casady

doi:10.4028/www.scientific.net/MSF.457-460.1193

Paper Titles

Effect of Passivation on Device Stability and Gate Reverse Characteristics on 4H-SiC MESFETs
p.1177

Fabrication and Characterization of 4H-SiC Planar MESFET Using Ion- Implantation
p.1181

Deep Level Investigation by Current and Capacitance Transient Spectroscopy in 4H-SiC MESFETs on Semi-Insulating Substrates
p.1185

600V 4H-SiC RESURF-Type JFET
p.1189

Influence of Buffer Layer on DC and RF Performance of 4H SiC MESFET
p.1193

Design of 1.7 to 14 kV Normally-Off Trenched and Implanted Vertical JFET in 4H-SiC
p.1197

Optimization of Vertical Silicon Carbide Field Effect Transistors towards a Cost Attractive SiC Power Switch
p.1201

RF Performance and Reliability of SiC MESFETs on High Purity Semi-Insulating Substrates
p.1205

High Frequency Measurements and Simulations of SiC MESFETs up to 250°C
p.1209

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Influence of Buffer Layer on DC and RF Performance of 4H SiC MESFET

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Materials Science Forum (Volumes 457-460)

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1193-1196

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.457-460.1193

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Online since:

June 2004

Authors:

A.V. Los, Michael S. Mazzola, D. Kajfez, B.T. McDaniel, C.E. Smith, James W. Kretchmer, L.B. Rowland, Jeff B. Casady

Keywords:

Admittance, Carrier Trapping, Equivalent Circuit, Hysteresis, Output Characteristic, Vanadium

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