Design of 1.7 to 14 kV Normally-Off Trenched and Implanted Vertical JFET in 4H-SiC

L. X. Li and J. H. Zhao, "Design of 1.7 to 14 kV Normally-Off Trenched and Implanted Vertical JFET in 4H-SiC ", Materials Science Forum, Vols. 457-460, pp. 1197-1200, 2004

Online since:

June 2004

Authors:

Larry X. Li, Jian Hui Zhao

Keywords:

Numerical Simulation, Silicon Carbide (SiC), Vertical JFET

Export:

RIS, BibTeX

Price:

$38.00

Permissions:

Request Permissions

Add to Cart

References

[1] J. A. Cooper, Jr., M. R. Melloch, R. Singh, A. Agarwal, and J. W. Palmour: IEEE Trans. Electron Devices, Vol. 49 (2002), p.665.

[2] M. M. Maranowski and J. A. Cooper, Jr.: IEEE Trans. Electron Devices, Vol. 46 (1999), p.520.

[3] P. Friedrichs, H. Mitlehner, R. Schörner, K. -O. Dohnke, R. Elpelt, and D. Stephani, Materials Science Forum, 2002, vols. 389-393, pp.1185-1188.

DOI: https://doi.org/10.4028/www.scientific.net/msf.389-393.1185

[4] K. Asano, Y. Sugawara, S. Ryu, R. Singh, J. Palmour, T. Hayashi, and D. Takayama, ISPSD 2001, pp.23-26.

[5] J. H. Zhao, X. Li, K. Tone, P. Alexandrov, M. Pan and M. Weiner: Solid-State Electronics, Vol. 47 (2003), pp.377-384.

[6] J. H. Zhao, K. Tone, X. Li, P. Alexandrov, L. Fursin and M. Weiner : ISPSD 2003, Cambridge, UK, pp.50-53.

Paper TitlePages

4H-SiC VJFETs with Self-Aligned Contacts

Authors: Konstantinos Zekentes, Antonis Stavrinidis, George Konstantinidis, Maria Kayambaki, Konstantinos Vamvoukakis, Emmanouil Vassakis, Konstantin V. Vasilevskiy, Alton B. Horsfall, Nick G. Wright, Pierre Brosselard, Shi Qin Niu, Mihai Lazar, Dominique Planson, Dominique Tournier, Nicolas Camara, Matthias Bucher

Abstract: Trenched-implanted-gate 4H–SiC vertical-channel JFET (TI-VJFET) have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. The effect of the channel geometry on the electrical characteristics has been studied by varying its length (0.3 and 1.2μm) and its width (1.5-5μm). The transistors exhibited high current handling capabilities (Direct Current density 330A/cm²). The output current reduces with the increase of the measurements temperature due to the decrease of the electron mobility value. The voltage breakdown exhibits a triode shape, which is typical for a static-induction transistor operation.

793

4H-SiC n-Channel DMOS IGBTs on (0001) and (000-1) Oriented Lightly Doped Free-Standing Substrates

Authors: Sauvik Chowdhury, Collin W. Hitchcock, Rajendra Dahal, Ishwara B. Bhat, T. Paul Chow

Abstract: We experimentally demonstrate 4H-SiC n-channel, DMOS Insulated Gate Bipolar Transistors (IGBTs) on 180 µm thick lightly doped free-standing n^- substrates with an ion-implanted collector region, and metal-oxide-semiconductor (MOS) gate on (0001) and (000-1) surfaces. The IGBTs show an on-state current of 20A/cm² at a power dissipation of 300W/cm². Threshold voltage of 7.5V and 10.5V was obtained on Si-face and C-face respectively. Both IGBTs show a small positive temperature coefficient of the forward voltage drop, which is useful for easy parallelization of devices.

954