4H-SiC DMOSFETs Processed Using Graphite Capped Implant Activation Anneal

Jeffery B. Fedison; Chris S. Cowen; Jerome L. Garrett; E.T. Downey; James W. Kretchmer; R.L. Klinger; H.C. Peters; Jesse B. Tucker; Kevin Matocha; L.B. Rowland; Steve Arthur

doi:10.4028/www.scientific.net/MSF.527-529.1265

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HomeMaterials Science ForumMaterials Science Forum Vols. 527-5294H-SiC DMOSFETs Processed Using Graphite Capped...

4H-SiC DMOSFETs Processed Using Graphite Capped Implant Activation Anneal

Abstract:

Results of a 1200V 4H-SiC vertical DMOSFET based on ion implanted n+ source and pwell regions are reported. The implanted regions are activated by way of a high temperature anneal (1675°C for 30 min) during which the SiC surface is protected by a layer of graphite. Atomic force microscopy shows the graphite to effectively prevent surface roughening that otherwise occurs when no capping layer is used. MOSFETs are demonstrated using the graphite capped anneal process with a gate oxide grown in N2O and show specific on-resistance of 64 mW×cm2, blocking voltage of up to 1600V and leakage current of 0.5–3 ´10-6 A/cm2 at 1200V. The effective nchannel mobility was found to be 1.5 cm2/V×s at room temperature and increases as temperature increases (2.8 cm2/V×s at 200°C).

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Periodical:

Materials Science Forum (Volumes 527-529)

Pages:

1265-1268

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.527-529.1265

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Online since:

October 2006

Authors:

Jeffery B. Fedison, Chris S. Cowen, Jerome L. Garrett, E.T. Downey, James W. Kretchmer, R.L. Klinger, H.C. Peters, Jesse B. Tucker, Kevin Matocha, L.B. Rowland, Steve Arthur

Keywords:

DMOSFET, Graphite Cap, Implant Activation Anneal, Ion Implantation

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References

[1] V.V. Afanas'ev, A. Stesmans, F. Ciobanu, G. Pensl, K.Y. Cheong, and S. Dimitrijev: Appl. Phys. Lett, Vol. 82, No. 4 (2003), pp.568-570.

DOI: 10.1063/1.1532103

Google Scholar

[2] Dr. James Scofield, U.S. Air Force Research Laboratory, private communication.

Google Scholar

[3] Y. Negoro, K. Katsumoto, T. Kimoto, and H. Matsunami: J. Appl. Phys, Vol. 96, No. 1 (2004), pp.224-228.

Google Scholar

[4] The NO anneal was performed courtesy of Professor John Williams, Auburn University.

Google Scholar

[1] 00. 0 1. 0 2. 0 3. 0 4. 0 5. 0 6. 0 7. 0 8. 0 VDS (V) IDS (A) VGS=50V VGS=60V VGS=40V VGS=30V VGS=20V.

DOI: 10.2135/cropsci1995.0011183x003500060044x

Google Scholar

[1] 00. 0 1. 0 2. 0 3. 0 4. 0 5. 0 6. 0 7. 0 8. 0 VDS (V) IDS (A) VGS=50V VGS=60V VGS=40V VGS=30V VGS=20V.

DOI: 10.2135/cropsci1995.0011183x003500060044x

[1] 0E-09.

[1] 0E-08.

[1] 0E-07.

[1] 0E-06.

[1] 0E-05.

[1] 0E-04 0 200 400 600 800 1000 1200 1400 1600 1800 VDS (V) IDS (A/cm 2) (-10, -5) (-11, -3) (-11, -5) (-12, -5) (-13, -5) (-8, -3) (-9, -3) (-9, -4) Fig. 4. Forward on-state current-voltage Fig. 5. Blocking current-voltage characteristics characteristics of fabricated 0. 02 cm 2 DMOSFET. of fabricated 0. 02 cm 2 DMOSFET.

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