Optimum Design of Short-Channel 4H-SiC Power DMOSFETs

Asmita Saha; James A. Cooper

doi:10.4028/www.scientific.net/MSF.527-529.1269

Paper Titles

Time Domain and Frequency Analysis of Random Telegraph Signal and the Contributions of G-R Centres to I-V Instabilities in 4H-SiC MESFETs
p.1251

SiC Power MOSFETs – Status, Trends and Challenges
p.1255

Development of 8 mΩ-cm², 1.8 kV 4H-SiC DMOSFETs
p.1261

4H-SiC DMOSFETs Processed Using Graphite Capped Implant Activation Anneal
p.1265

Optimum Design of Short-Channel 4H-SiC Power DMOSFETs
p.1269

Realization of Large Area Vertical 3C-SiC MOSFET Devices
p.1273

High Power-Density 4H-SiC RF MOSFETs
p.1277

4.3 mΩcm², 1100 V 4H-SiC Implantation and Epitaxial MOSFET
p.1281

Fabrication and Performance of 1.2 kV, 12.9 mΩcm² 4H-SiC Epilayer Channel MOSFET
p.1285

HomeMaterials Science ForumMaterials Science Forum Vols. 527-529Optimum Design of Short-Channel 4H-SiC Power...

Optimum Design of Short-Channel 4H-SiC Power DMOSFETs

Abstract:

We describe an optimized design for the 1 kV short-channel 4H-SiC power DMOSFET, obtained from numerical simulations using the Taguchi method. Three new structural features are employed: (1) a current spreading layer (CSL) below the p-well, (2) a heavily-doped, narrow JFET region, and (3) a segmented p-well contact.