Optimum Design of Short-Channel 4H-SiC Power DMOSFETs

Abstract:

Article Preview

We describe an optimized design for the 1 kV short-channel 4H-SiC power DMOSFET, obtained from numerical simulations using the Taguchi method. Three new structural features are employed: (1) a current spreading layer (CSL) below the p-well, (2) a heavily-doped, narrow JFET region, and (3) a segmented p-well contact.

Info:

Periodical:

Materials Science Forum (Volumes 527-529)

Edited by:

Robert P. Devaty, David J. Larkin and Stephen E. Saddow

Pages:

1269-1272

Citation:

A. Saha and J. A. Cooper, "Optimum Design of Short-Channel 4H-SiC Power DMOSFETs", Materials Science Forum, Vols. 527-529, pp. 1269-1272, 2006

Online since:

October 2006

Export:

Price:

$38.00

[1] M. Matin, A. Saha, and J. A. Cooper, Jr.: IEEE Trans. Electron Devices, Vol. 51 (2004), p.1721.

[2] R. K. Roy: Design of Experiments Using the Taguchi Approach: 16 Steps to Product and Process Improvement (John Wiley and Sons, New York 2001).

Fetching data from Crossref.
This may take some time to load.