Improved 4H-SiC MOS Interfaces Produced via Two Independent Processes: Metal Enhanced Oxidation and 1300°C NO Anneal

Mrinal K. Das; Brett A. Hull; Sumi Krishnaswami; Fatima Husna; Sarah K. Haney; Aivars J. Lelis; Charles Scozzie; James D. Scofield

doi:10.4028/www.scientific.net/MSF.527-529.967

Paper Titles

Si/SiO₂ and SiC/SiO₂ Interfaces for MOSFETs – Challenges and Advances
p.935

Nitrogen and Hydrogen Induced Trap Passivation at the SiO₂/4H-SiC Interface
p.949

Impact of Dislocations on Gate Oxide in SiC MOS Devices and High Reliability ONO Dielectrics
p.955

High Channel Mobility 4H-SiC MOSFETs
p.961

Improved 4H-SiC MOS Interfaces Produced via Two Independent Processes: Metal Enhanced Oxidation and 1300°C NO Anneal
p.967

Characterization of 4H-SiC MOSFETs with NO-Annealed CVD Oxide
p.971

Investigation of SiO₂-SiC Interface by High-Resolution Transmission Electron Microscope
p.975

Interfacial Properties of SiO₂ Grown on 4H-SiC: Comparison between N₂O and Wet O₂ Oxidation Ambient
p.979

Effect of Reactive-Ion Etching on Thermal Oxide Properties on 4H-SiC
p.983

HomeMaterials Science ForumMaterials Science Forum Vols. 527-529Improved 4H-SiC MOS Interfaces Produced via Two...

Improved 4H-SiC MOS Interfaces Produced via Two Independent Processes: Metal Enhanced Oxidation and 1300°C NO Anneal

Abstract:

Two previously reported MOS processes, oxidation in the presence of metallic impurities and annealing in nitric oxide (NO), have both been optimized for compatibility with conventional 4H-SiC DMOSFET process technology. Metallic impurities are introduced by oxidizing in an alumina environment. This Metal Enhanced Oxidation (MEO) yields controlled oxide thickness (tOX) and robustness against high temperature processing and operation while maintaining high mobility (69 cm2/Vs) and near ideal NMOS C-V characteristics. Raising the NO anneal temperature from 1175oC to 1300oC results in a 67% increase in the mobility to 49 cm2/Vs with a slight stretch-out in the NMOS C-V. Both processes exhibit a small 30% mobility reduction in MOSFETs fabricated on NA = 1x1018 cm-3 implanted p-wells. The low field mobility in the MEO MOSFETs is observed to increase dramatically with measurement temperature to 160 cm2/Vs at 150oC.

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Silicon Carbide and Related Materials 2005

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Materials Science Forum (Volumes 527-529)

Pages:

967-970

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.527-529.967

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Online since:

October 2006

Authors:

Mrinal K. Das, Brett A. Hull, Sumi Krishnaswami, Fatima Husna, Sarah K. Haney, Aivars J. Lelis, Charles Scozzie, James D. Scofield

Keywords:

Channel Mobility, Interface States (or Traps), MEO, Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), MOS, Nitridation, Oxidation

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References

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