3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide

Motoki Kobayashi; Hidetsugu Uchida; Akiyuki Minami; Toyokazu Sakata; Romain Esteve; Adolf Schöner

doi:10.4028/www.scientific.net/MSF.679-680.645

Paper Titles

Optimization of SiC MESFET for High Power and High Frequency Applications
p.629

1700V, 20A 4H-SiC DMOSFETs Optimized for High Temperature Operation
p.633

4kV Silicon Carbide MOSFETs
p.637

A Comparison of 1200 V Normally-OFF & Normally-on Vertical Trench SiC Power JFET Devices
p.641

3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide
p.645

Comparison of Total Losses of 1.2 kV SiC JFET and BJT in DC-DC Converter Including Gate Driver
p.649

Fabrication of P-Channel MOSFETs on 4H-SiC C-Face
p.653

Use of Vacuum as a Gate Dielectric: The SiC VacFET
p.657

980 V, 33A Normally-Off 4H-SiC Buried Gate Static Induction Transistors
p.662

HomeMaterials Science ForumMaterials Science Forum Vols. 679-6803C-SiC MOSFET with High Channel Mobility and CVD...

3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide

Abstract:

3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.