Materials Science Forum Vols. 717-720

Abstract: A reduced growth pressure (down to 10 Torr) was employed for the low-temperature chloro-carbon epitaxial growth. More than two times lower H₂ flow rate became possible. The optimal input H₂/Si and C/Si ratios were also lower. A significant reduction of the net free donor concentration resulted from the use of the low pressure, delivering partially compensated epilayers with the net free donor concentration below 7x10¹³ cm^-3. Deep levels were characterized in the low-temperature epilayers for the first time. No Z_1/2 or EH_6/7 centers could be detected by DLTS. No strong D₁ photoluminescence signature was observed. The high purity of the obtained epitaxial layers made it possible to use the low-temperature chloro-carbon epitaxial growth to fabricate drift regions of Schottky diodes for the first time. Promising values of the reverse breakdown voltage and the leakage current were obtained from the fabricated devices.

Abstract: Vanadium doping from SiCl4 source during epitaxial growth with chlorinated C and Si precursors was investigated as a mean of achieving compensated and semi-insulating epitaxial 4H-SiC layers for device applications. Thin epilayers were grown at 1450°C with a growth rate of ~6 μm/h. Experiments at 1600°C resulted in the growth rates ranging from 60 to 90 µm/h producing epilayers with thickness above 30 µm. V concentrations up to about 10¹⁷cm^-3 were found safe for achieving defect-free epilayer surface morphology, however certain degradation of the crystalline quality was detected by XRD at V concentrations as low as 3-5x10¹⁵ cm^-3. Controllable compensation of nitrogen donors with V acceptors provided low-doped and semi-insulating epitaxial layers. Mesa isolated PiN diodes with V-acceptor-compensated n- epilayers used as drift regions showed qualitatively normal forward- and reverse-bias behavior.

Abstract: This paper reports the progress of the thick epitaxy development at Dow Corning. Epiwafers with thickness of 50 – 100 m have been grown on 4° off-axis 76mm 4H SiC substrates. Smooth surface with RMS roughness below 1nm and defect density down to 2 cm-2 are achieved for 80 - 100 m thick epiwafers. Long carrier lifetime of 2 – 4 s are routinely obtained, and low BPD density in the range of 50 down to below 10 cm-2 is confirmed. High voltage JBS diodes have been successfully fabricated on these wafers with thick epitaxial layers.

Abstract: In this study, we struck a balance between specular surface morphology and polytype homogeneity on an epitaxial layer grown on 4H-SiC Si-face substrate with off angle less than 1degree by controlling the C/Si ratio with the SiH₄ flow rate. Schottky barrier diodes fabricated on a grown epitaxial layer exhibited a blocking of voltage over 1000 V and an n value of less than 1.1 with a high yield of more than 80%. A substrate with a low off angle was found to have an advantage as regareds the stress that generates the interfacial dislocations at the epitaxial layer/substrate interface during the epitaxial growth process.

Abstract: Chemical vapour deposition in a cold wall reactor working at atmospheric pressure was used to study the homoeptaxial growth of 4H-SiC on 4°ff misoriented substrates from silane and propane precursors. The effect of various growth parameters (temperature 1450-1650°C, C/Si ratio 1-7, thickness 2.5-10 µm) were studied in order to determine the best conditions for obtaining smooth surfaces after epitaxy. It is shown that the main source of roughness is surface undulation which easily appears during growth, especially at low C/Si ratios and high temperature (up to 1600°C). Temperatures above 1600°C and C/Si ratio of 1 give the best results. When reducing temperature, a trade-off has to be found between defects formation and surface undulation.

Abstract: In this paper we study the surface morphology of <11-20> 4° degree off, silicon terminated, 4H Silicon Carbide (4H-SiC) in terms of growth parameters and post growth argon thermal annealing. We find that out-of-equilibrium conditions favor the reduction of the surface roughness. Furthermore, we find preliminary indications that the same growth parameters that lead to the reduction of the surface roughness promote also a reduction of (1,3) and (4,4) stacking faults density.

Abstract: Formation of particles and their effect on SiC epitaxial growth in the CVD reactor is investigated. Particle induced defects in the epilayer at different gas decomposition conditions are discussed. A higher number of pits with larger diameters are observed in the epilayer for conditions where gases decompose later in the gas injector tube (i.e. nearer to the substrate). On the other hand, the number and size of these pits reduce for the condition where gas decomposes earlier in the tube. To investigate the effect of particles during the growth, various particles with different size, shape and compositions are intentionally placed on the substrate surface before epitaxial films are grown. Samples are mapped and compared at similar locations in the pre-growth, post growth and post-etch (by molten KOH) conditions. It is found that the nature of particle induced defects depends primarily on size and shape of particles.

Abstract: In this report we present homoepitaxial growth of 4H-SiC on Si-face, nominally on-axis substrates with diameters up to 76 mm in a hot-wall chemical vapor deposition reactor. A comparatively low carrier lifetime has been observed in these layers; local variations in carrier lifetime are different from standard epilayers on off-cut substrates. The properties of the layers were studied with focus on charge carrier lifetime and its correlation with starting growth conditions, inhomogeneities of surface morphology and different growth mechanisms.

Abstract: Carrier lifetime has been studied as a function of C/Si ratio and growth rate during epitaxial growth of n-type 4H-SiC using horizontal hot-wall CVD. Effort has been put on keeping all growth parameters constant with the exception of the parameter that is intended to vary. The carrier lifetime is found to decrease with increasing growth rate and the highest carrier lifetime is found for a C/Si ratio of 1. The surface roughness was correlated with epitaxial growth conditions with AFM analysis.

Abstract: In this work we report on SiC epitaxial growth by vapour-liquid-solid (VLS) mechanism on on-axis 4H-SiC(0001) substrates which were previously patterned to form mesa structures. The liquid phase was set to Al70Si30. At 1100°C, it led to very high homoepitaxial lateral growth (140 µm/h) with pronounced spiral growth and in plane anisotropy of growth rate. Upon temperature increase to 1200 °C, this spiral growth was suppressed and the lateral growth was further increased up to 180 µm/h. The in-plane versus out-of-plane anisotropy of growth rate was found to be as high as 60 at this temperature and 46 at 1100°C.