Optimization of Holding Current in 4H-SiC Thyristors

Stanislav Soloviev; Ahmed Elasser; Sarah Katz; Steve Arthur; Zach Stum; Liang Chun Yu

doi:10.4028/www.scientific.net/MSF.740-742.994

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HomeMaterials Science ForumMaterials Science Forum Vols. 740-742Optimization of Holding Current in 4H-SiC...

Optimization of Holding Current in 4H-SiC Thyristors

Abstract:

Two designs (A and B) of 4H-SiC thyristors for pulse power applications were implemented and characterized in this work. Both designs have the same layout and epi-layer stack except for the anode layers: thyristors with design A (baseline) had a thin (~0.5 um) anode while devices with design B (optimized) consisted of a heavily doped cap layer (~0.5 um, ~10¹⁹/cc) and ~1.5 um p-type layer with lower doping (~1018/cc). All devices were fabricated in 4” 4H-SiC sub^{Superscript text}strates (three wafers per each design) and were fully characterized at the wafer level including measurements of forward voltage, blocking voltage, leakage current, and holding current. It was shown that the mean value of the holding current in the thyristors with thin anode was significantly higher (0.7A) than that of the thyristors with thick anode (0.1A), while other parameters had practically the same values. The open circuit voltage decay (OCVD) method was used for measurements of the minority carrier lifetime in order to correlate it with the holding current. Impact of material properties and device design parameters on the holding current is discussed as well.

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Periodical:

Materials Science Forum (Volumes 740-742)

Pages:

994-997

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.740-742.994

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Online since:

January 2013

Authors:

Stanislav Soloviev, Ahmed Elasser, Sarah Katz, Steve Arthur, Zach Stum, Liang Chun Yu

Keywords:

Carrier Lifetime, Pulse Power, Silicon Carbide (SiC), Substrate Defects, Thyristor

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References

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