Materials Science Forum Vols. 740-742

Abstract: In this paper, micro-Raman characterizations and Finite element modeling (FEM) of microstructures (cantilever, bridge, planar rotating probe) realized on single-crystal (100) 3C-SiC/Si films are performed. Transverse optical (TO) Raman mode analysis reveals the stress relaxation on the free standing structure (796.5 cm-1) respect to the stressed unreleased region (795.7 cm-1). The TO Raman mode exhibits an intense shift, up to 2 cm-1, located on the undercut region, where the Silicon substrate starts to be released. Such effect is ascribed to the modification of the Raman stress tensor that makes the generalized axial regime, described by diagonal components of the Raman stress tensor, unsuitable to describe the stress status on this region. Raman maps analysis and FEM simulations show the “activation” of the shear stress, i.e. non-diagonal components of the stress tensor. The aim of future works will be to minimize the stress field generation and the defects density within the epitaxial layer.

Abstract: Abstract. In the present paper we attempt to study and explain the increased leakage currents in Schottky diodes with an integrated p-n-structure. By a scanning Kelvin probe method (vibrating capacitor) were obtained the local variations of surface contact potential difference (CPD) for the chips with large and small leakage currents. It is shown that samples with higher leakage currents have smaller surface potential barrier. The SEM investigations revealed that a critical role in increasing leakage currents play the dislocations penetrating from the substrate into the epitaxial layer.

Abstract: A 4H-SiC trench MOSFET has been developed that features trench gates with a thick oxide layer on the bottoms of the trenches. The maximum electric field strength and gate-drain charge of this device are 46% and 38%, respectively lower than that of a conventional MOSFET. The drain-source breakdown voltage is 1400V and the specific on-resistance is 4.4mΩcm2 at a gate bias of 20V and a drain voltage of 2V.

Abstract: A 4H-SiC TMBS diode with improved trench corners has been demonstrated. The trench profiles are improved by using 12sccm/28sccm of SF6/Ar mixture, and a working pressure of 12 mtorr for RIE etching. The depth of micro-trenching has been reduced to lower than 0.07 μm. The 4H-SiC TMBS diode with improved trench profiles shows a breakdown voltage over 725V.

Abstract: This study focuses on the characterization of silicon dioxide (SiO₂) layers, either thermally grown or deposited on trenched 100 mm 4H-silicon carbide (SiC) wafers. We evaluate the electrical properties of silicon dioxide as a gate oxide (GOX) for 3D metal oxide semiconductor (MOS) devices, such as Trench-MOSFETs. Interface state densities (D_IT) of 1_*10¹¹ cm^-2 eV^-1 under flat band conditions were determined using the hi-lo CV-method [1]. Furthermore, current-electric field strength (IE) measurements have been performed and are discussed. Trench-MOS structures exhibited dielectric breakdown field strengths up to 10 MV/cm.

Abstract: Metal-oxide-semiconductor (MOS) capacitors with phosphorus localized near the SiO₂/SiC interface were fabricated on 4H-SiC by direct POCl₃ treatment followed by SiO₂ deposition. Post-deposition annealing (PDA) temperature affected MOS device properties and phosphorus distribution in the oxide. The sample with PDA at 800 °C showed narrow phosphorus-doped oxide region, resulting in low interface state density near the conduction band edge and small flatband voltage shift after FN injection. The interfacial localization of phosphorus improved both interface properties and reliability of 4H-SiC MOS devices.

Abstract: In this work the field effect mobility measured on lateral n-channel MOSFETs in 4H-SiC with Al implanted body was correlated with the interface trap density measured on MOS capacitors. The test devices were fabricated on samples subjected to different post implantation annealing conditions (i.e. with or without a protective carbon capping layer) and to an identical post-oxidation annealing in N₂O. Despite the improved interfacial morphology, a reduction of the peak mobility (from 40 to 24 cm²V^-1s^-1) was observed using the carbon capping layer. An increase in the density of interface traps was consistently found. Nanoscale measurements of the active dopant concentration in the SiC channel region by cross-sectional scanning capacitance microscopy showed an higher compensation of p-type SiC for the sample processed without the capping layer, which indicates a more efficient incorporation of nitrogen at the SiO₂/SiC interface.

Abstract: In the present work, we studied the influence of the post-implantation annealing temperature on the performance and oxide reliability of lateral 4H-SiC MOSFETs. The maximum field effect mobility of the MOSFETs at 25°C decreases from 22.4cm²/Vs to 17.2cm²/Vs by increasing annealing temperature from 1600°C to 1800°C. Respectively, the measured meantime to failure is about one order of magnitude higher for the 1700°C annealed sample at an applied field of 8.5MV/cm compared to the 1600°C and 1800°C annealed samples.

Abstract: MOSFETs and capacitors have been fabricated to investigate the atomic layer depositon (ALD) of SiO₂ onto SiC compared to thermal oxidation of SiC. Devices were fabricated on 4H-SiC with the following oxidation treatments: thermal oxidation at 1175°C, thermal oxidation at 1175°C followed by a nitric oxide (NO) anneal at 1175°C, and ALD of SiC at 150°C followed by an NO post oxidation anneal (POA) at 1175°C. ALD of the SiO₂ was performed using 3-aminopropyltriethoxysiliane (3-APTES), ozone and water. Capacitors fabricated with NO annealed ALD oxide and thermal oxide with NO POA exhibited similar CV behavior and yielded similar Dit of 1e11 at 0.5 eV from the conduction band. MOSFETs fabricated with NO PDA ALD oxide exhibited peak field effect mobilities ranging from 32 – 40.5 cm2/Vs compared to 30 –34.5 cm2/Vs for the MOSFETs with NO annealed thermal oxide. The higher mobilities exhibited by the ALD gate oxides were linked through SIMS to higher nitrogen concentrations at the SiO₂/SiC interface.

Abstract: Two-dimensional device simulations of 4H-SiC DMOSFET were performed in this study. Two types of P-Well doping profiles are compared. The retrograde profile can have higher breakdown voltage as compared to the box profiles. The P-well concentration is also examined and optimized. The DMOS device can have a better avalanche behavior once the P-Well concentration is higher than 2E18 cm-3. In addition, the interfacial oxide effect on the channel mobility has also been studied. The interfacial charge density should be controlled to lower than 2E11 cm-2 so as to have a higher mobility and lower on-state resistance.