Materials Science Forum Vols. 740-742

Abstract: While aluminum-based metallization schemes on Si have been optimized for the last decades, only few investigations have been done on copper metallization with SiC-devices. Thus, in this work the mechanical as well as the electrical interactions of this metallization system have been analyzed and optimized for SiC-devices in high reliability applications. For optimizing the adhesion of the copper metallization stack on SiC devices, different metallization schemes consisting of adhesion promoters (Ti, Cr, Al, Ta, WTi), diffusion barriers (TiN, Ta, WTi), and the final copper layer have been tested by peel-tests. For investigating the electrical interactions TLM measurements as well as leakage-current measurements have been done on copper metalized SiC samples.

Abstract: The SiO₂ layer was deposited on the 4H-SiC Si face by the thermal decomposition of tetraethylorthosilicate(TEOS) in N₂ atmosphere to from MIS diodes. The post deposition annealing was effective to improve the interface properties. The interface state density of the deposited SiO₂/SiC MIS structure was estimated to be the order of 10¹¹ cm^-2eV^-1 by Terman method. The direct nitridation of SiC surface prior to the deposition of the SiO₂ layer was effective to reduce the interface state density.

Abstract: Silicon carbide (SiC) is one of the most attractive semiconductors for high voltage applications. The breakdown voltage of SiC-based devices highly depends on the variation of the fabrication process including doping of the epilayers and the etching steps. In this paper, we show a way to diminish this variability by employing novel trench structures. The influence of the process variations in terms of doping concentration and etching has been studied and compared with conventional devices. The breakdown voltage variation (ΔVBR) of 450 V and 2100 V is obtained for the ±20% variation of doping concentration of the devices with and without the trench structures, respectively. For ±20% variation in etching steps, the maximum ΔVBR of 380 V is obtained for the device with trench structures in comparison to 1800 V for the conventional structure without trench structures. These results show that the breakdown voltage variation is significantly reduced by utilizing the proposed structure.

Abstract: Silicon carbide (SiC) is a promising semiconductor material for high-temperature, high-frequency, high-power, and energy-saving applications. However, because the hardness and chemical stability of SiC are high, few conventional machining methods can handle this material efficiently. We previously developed a plasma chemical vaporization machining (PCVM) technique, which is an atmospheric-pressure plasma etching process, and investigated its application to the processing of SiC substrates. In this paper, we propose a novel style of PCVM technique for dicing, using slit apertures to confine the plasma. From experiments by means of an apparatus with a one-slit aperture formed by two masks, it was found that the kerf loss was almost proportional to the slit width, and that the etching depth increased with RF power. Furthermore, from experiments on a SiC wafer, we obtained a 130-μm etching depth and 300-μm kerf loss for an 11-min processing time and 200-μm slit width.

Abstract: A comprehensive study on different polytypes (α-SiC and β-SiC) and crystal orientations ((0001) and (11-20) of 6H-SiC) has been investigated in order to elaborate Silicon carbide (SiC) nanopillar using inductively coupled plasma etching method. The SiC nanopillars with the cross section of rhombus, pentagon, and hexagonal have been obtained on β-SiC (001), misoriented α-SiC (11-20), and α-SiC (0001) on-axis substrates, respectively. It was found that crystal orientations and polytypes play key roles for the morphology of SiC nanopillars, which reflects the so-called Wulff's rule.

Abstract: DNA biosensors based on silicon carbide nanowire bioFET (SiC NW bioFET) benefit from both biocompatibility and semiconducting properties of SiC. One of the device realization key points is the functionalization of the SiC NW. This process is composed of two main steps: silanization and DNA grafting. It has been successfully carried out on both SiC single crystals and SiC nanopillars. Evidences of DNA detection are given by X-Ray photoelectron Spectroscopy (XPS) and fluorescence microscopy.

Abstract: Due to its inert chemical nature, plasma etching is the most effective technique to pattern SiC. In this paper, dry etching of 4H-SiC substrate in Inductively Coupled Plasma (ICP) has been studied in order to evaluate the impact of process parameters on the characteristics of etching such as etch rate and trenching effect. Key process parameters such as platen power and ICP coil power prove to be essential to control the SiC etch rate. On the other hand, the ICP coil power and the working pressure mainly master the trenching effect. Our results enlighten that high etch rate with minimal trenching effect can be obtained using high ICP coil power and low working pressure.

Abstract: To solve the problem that no preferential chemical etching is available for dislocation revelation from the carbon-face (C-face) of 4H-SiC, a novel etching technique using vaporized KOH has been developed. It was found that this etching technique can reveal the three commonly found dislocation types, i.e., threading screw dislocations (TSDs), threading edge dislocations (TEDs) and basal plane dislocations (BPDs) as large hexagonal, small hexagonal and triangular, respectively. Centimeter-scale dislocation mapping has been obtained, and the pit positions on the C-face were compared with those on the Si-face, to study the dislocation propagation behaviors across the sample thickness. We have found one-to-one correlation for nearly 96% of the TSDs, indicating a dominant proportion of TSDs penetrate the whole wafer thickness. The vaporized KOH etching technique has provided an effective and inexpensive method of making inch-scale mapping of dislocation distribution for the C-face epitaxial and bulky 4H-SiC.

Abstract: We found that the ‘Si and C emission model’ that we proposed as an oxidation model of SiC could not reproduce the initial oxide growth rates of SiC at sub-atmospheric pressures. The comparison between calculated and observed growth rates suggests that the oxide growth on the oxide surface is enhanced in the initial oxidation stage and thus our oxidation model is inaccurate in the description on the surface oxidation. Accordingly, we reconsidered the parameters on surface oxidation and, as a result, found that a much enlarged oxygen concentration on the oxide surface is necessary for solving the discrepancy between calculated and observed growth rates.

Abstract: In this work SiC-based MIS capacitors have been fabricated with different contact/high-k dielectric combinations and the temperature dependence of the characteristics have been examined in an N₂ ambient at temperatures between 323K and 673K. The structures utilise either a Pt or Pd catalytic gate contact and a TiO₂ or HfO₂ high-k dielectric, all of which are grown on a thin SiO₂ layer, thermally grown on the Si face of a 4H SiC epitaxial layer. The MIS capacitors have been studied in an N2 ambient between 323K and 673K and observations show that V_FB reduces with increasing temperature. The majority of this variation is caused a reduction in the D_it influencing the structures electrical characteristics, due to a shift in the semiconductors bulk potential, which is due to the lower V_TH of SiC-based MOSFETs at high temperatures.