Materials Science Forum Vols. 740-742

Abstract: The reduction of reverse leakage currents was attempted to fabricate 4H-SiC diodes with large current capacity for high voltage applications. Firstly diodes with Schottky metal of titanium (Ti) with active areas of 2.6 mm2 were fabricated to investigate the mechanisms of reverse leakage currents. The reverse current of a Ti Schottky barrier diode (SBD) is well explained by the tunneling current through the Schottky barrier. Then, the effects of Schottky barrier height and electric field on the reverse currents were investigated. The high Schottky barrier metal of nickel (Ni) effectively reduced the reverse leakage current to 2 x 10-3 times that of the Ti SBD. The suppression of the electric field at the Schottky junction by applying a junction barrier Schottky (JBS) structure reduced the reverse leakage current to 10-2 times that of the Ni SBD. JBS structure with high Schottky barrier metal of Ni was applied to fabricate large chip-size SiC diodes and we achieved 30 A- and 75 A-diodes with low leakage current and high breakdown voltage of 4 kV.

Abstract: N-LDMOS and n-LIGBT structures were manufactured with the same dimensions on a 4H-SiC wafer in order to allow for a direct comparison. The comparison of the devices includes output and transfer characteristics, blocking characteristics, and temperature behavior.

Abstract: The development of silicon carbide complimentary metal-oxide-semiconductor (CMOS) is a key-enabling step in the realisation of low power circuitry for high-temperature applications. This paper describes investigations using the charge pumping technique into the properties of the gate dielectric interface as part of the development of the technology to realise monolithic fabrication of both n and p channel devices. A comparison of the charge pumping technique and the Hill-Coleman and Terman methods is also carried out to explore the feasibility of the technique.

Abstract: In this work, we report our recently developed 16 kV, 1 cm², 4H-SiC PiN diode results. The SiC PiN diode was built on a 120 µm, 2×10¹⁴/cm³ doped n-type SiC drift layer with a device active area of 0.5175 cm². Forward conduction of the PiN diode was characterized at temperatures from 20°C to 200°C. At high injection-current density (J_F) of 350 ~ 400 A/cm², the differential on-resistance (R_ON,diff) of the SiC PiN diode decreased from 6.08 mΩ·cm² at 20°C to 5.12 mΩ·cm² at 200°C, resulting in a very small average temperature coefficient of –5.33 µΩ·cm²/°C, while the forward voltage drop (V_F) at 100 A/cm² reduced from 4.77 V at 20°C to 4.17 V at 200°C. This is due to an increasing high-level carrier lifetime with an increase in temperature, resulting in reduced forward voltage drop. We also observed lower R_ON,diff at higher injection-current densities, suggesting that a higher carrier lifetime is needed in this lightly doped n-type SiC thick epi-layer in order to achieve full conductivity modulation. The anode to cathode reverse blocking leakage current was measured as 0.9 µA at 16 kV at room temperature.

Abstract: 4H-SiC PiN diodes for 6.5 kV were manufactured on both 4° and 8° off-cut substrates and subjected to an electrical stress test on wafer level and subsequent analysis of structural defects present in the active area of the diodes. For 8° off-cut diodes, the electrical characteristics with respect to leakage current and forward voltage drift are worse than the electrical characteristics of 4° off-cut diodes. Furthermore, a large number of stacking faults was found in 8° off-cut diodes, but little evidence for bipolar degradation was found in 4° off-cut diodes. Therefore, bipolar degradation was significantly reduced by avoiding BPDs in the active area of PiN diodes, i.e. by the use of 4° off-cut substrates. Furthermore, a strong correlation was found between the electrical screening test on wafer level and critical defects.

Abstract: The electrical characteristics of 4H-SiC pin diodes with 8H-type in-grown stacking faults are investigated. The pin diodes have epilayers with low Z_1/2 center concentration formed by using the carbon implantation process. The forward voltage drops of the diode with 8H-type in-grown stacking faults are larger than those of the diode without a 8H-type in-grown stacking fault. At room temperature, the differential on-resistance of the pin diode with 8H-type in-grown stacking faults is larger than the value calculated from donor concentration in the drift layer by using the current transportation model of the unipolar device. Meanwhile, the differential on-resistances of the pin diode with 8H-type in-grown stacking faults decrease with an increase in temperature and become smaller than the calculated value at temperature of more than 200 °C.

Abstract: 13-kV 4H-SiC PiN diodes were fabricated on 4° and 8° off-axis substrates and their electrical properties were examined. Small test PiN diodes with various JTE concentrations were fabricated and the dependence of JTE concentration was examined. The highest breakdown voltages were 14.6 and 14.1 kV at a JTE1 concentration of 1.9 × 10¹⁷ cm⁻³ for both the 4° and 8° off-axis substrates. Based on the results, 4 mm × 4 mm SiC PiN diodes were successfully fabricated and exhibited avalanche breakdown voltages of 14.0 and 13.5 kV for the 4° and 8° off-axis substrates, respectively. Forward voltage degradation was larger for the 8° off-axis substrates.

Abstract: This paper deals with electrical characterization of PiN diodes fabricated on an 8° off-axis 4H-SiC with a p⁺⁺ localized epitaxial area grown by Vapour-Liquid-Solid (VLS) transport. It provides for the first time evidence that a high quality p-n junction can be achieved by using this technique followed by a High Temperature Annealing (HTA) process.

Abstract: We report a 900V 4H-SiC depletion mode (DM) VJFET with a specific on-resistance (R_DSON,SP) of 1.46mOhm-cm² at V_GS=2.5V, I_DS=10A. The R_DSON,SP of the DM VJFET, designed for 600V-800V applications, is one of the lowest reported for a VJFET and is an order of magnitude lower compared to best Si Super Junction (SJ) MOSFETs reported in the literature. The turn-on (E_ON), turn-off (E_OFF) and total (E_TOTAL) switching energies of the DM-VJFET at VDD=400V, I_DS=32.5A are 146uJ, 168uJ and 314uJ respectively. The switching figure of merit R_DSON×Q_G is 3.8Ohm-nC; this is comparable to or better than the reported SJ-MOSFETs.

Abstract: A necessity for the successful commercialization of SiC power devices is their long term reliability under the switching conditions encountered in the field. Normally-ON 1200 V SiC JFETs were stressed in repetitive hard-switching conditions to determine their fault handling capabilities. The switching pulses were generated from an RLC circuit, where energy initially stored in capacitors discharges through the JFET into a resistive load. The hard-switching included one million repetitive pulsed hard-switching events at 25 °C from a drain blocking-voltage of 600-V to an on-state current of 67 A, and an additional one million 600-V/63-A pulsed hard-switching events at 150 °C. The JFET conduction and blocking-voltage characteristics are virtually unchanged after over two million hard switching events proving the devices are reliable for handling high surge-current faults like those encountered in bidirectional circuit breaker applications.°