Materials Science Forum Vols. 740-742

Abstract: A hybrid silicon-carbide junction-gate field-effect transistor (HJT: hybrid JFET) is proposed. The HJT consists of a silicon-carbide (SiC) normally-on vertical JFET and a low-voltage normally-off silicon metal-oxide-semiconductor field-effect transistor (Si-MOS: silicon MOSFET). These two devices are connected by bonding wire as a cascode circuit [1] and packaged in a TO-3P split-lead-frame package with the same pin arrangement as conventional silicon power devices, which can thus be easily replaced by the proposed HJT. The vertical JFET has a steep-junction deep-trench structure in its channel region. This structure gives a low on-state resistance of under 60 mΩ and breakdown voltage of over 600 V with the die size of 6.25 mm². Since the deep-trench structure also lowers the cutoff voltage of the JFET, required minimum breakdown voltage of the Si-MOS is reduced and on-state resistance of the Si-MOS is lowered. The HJT demonstrated on-state resistance of 69 mΩ and breakdown voltage of 783 V. These results indicate that the proposed HJT is a strong candidate for low-resistance high-power switching devices.

Abstract: Silicon Carbide (SiC) Junction-Field Effect Transistors (JFETs) are attractive devices for power electronics. Their high temperature capability should allow them to operate with a reduced cooling system. However, experiments described in this paper conclude to the existence of runaway conditions in which these transistors will reach destructive temperatures.

Abstract: Two sets of 4H-SiC signal-lateral JFETs were thermally aged at 400°C and 500°C in furnaces open to air for 1000 hours. I"-" V and low frequency noise measurements were performed on these devices and the results were compared against the as-fabricated sample. The data from I"-" V characterisation demonstrates that the linear and saturated drain-source current decreases monotonically with stress temperature. In addition, the linear characteristics of the JFETs have shifted approximately 1.5V along the drain-source voltage axis. Whilst the devices thermally aged at 400°C show no degradation in magnitude and behaviour in Noise Power Spectral Density (NPSD), the NPSD of 500°C stressed devices has increase approximately 30dB and it shows a full frequency spectrum of 1/ƒ dependency up to 100 kHz. A further investigation of the noise origin reveals that the Normalised Noise Power Spectral Density (NNPSD) of the aged sample is directly proportional to R_DS which is similar to the as-fabricated sample. Thus we hypothesize that the existing noise sources have intensified possibly due to the evolution of defects.

Abstract: This paper presents the methodology for the design of a novel 4H-SiC JFET structure able to sustain 3.3 kV. Comparisons between simulation and characterization res will be made. Taken into account the process limitation, we will also discuss the critical steps and their impact on the electrical characteristics. A design methodology based on Baliga's criterion is proposed to obtain the optimal structure. A 50 nm thick thermal oxide grown above vertical channel and the use of a buried p+ layer as second gate electrode are brand new in front of what is found in literature.

Abstract: The steady state characteristics of a normally-off 4H-SiC Bipolar Mode FET (BMFET) with a low on-resistance are investigated in a wide range of currents and temperatures by means of an intensive numerical simulation study which clarifies what are the main design constraints. Specific physical models and parameters strictly related to the presently available 4H-SiC technology are carefully taken into account. A drain forward current density up to 500 A/cm², a specific on-resistance lower than 2 mΩ∙cm² and a current gain in the order of a few tens are calculated. The blocking voltage is in excess of 1.3 kV with a low leakage current. These results are compared with the experimental data measured in the same test conditions of another SiC power device already introduced to the market.

Abstract: The paper discusses the switching performance of the double-gate SiC trench JFET. In applications such as dc/dc converters, when fast switching is expected the standard totem-pole driver is not sufficient. The reason for this is that both the internal resistance and the parasitic capacitances of this device are significantly higher than for other designs. Instead, the gate driver with a dynamic current source is proposed in this paper to speed-up the switching process. Performed double-pulse measurements show improved dynamic performance of the tested DGTJFET with the new driver.

Abstract: We compare the on-state and switching performance of a 600 V-class Hybrid SiC junction field effect transistor (HJT) and Si superjunction MOSFETs (SJ-MOSs), both of which are packaged in TO-3P full-mold package, as a function of operating frequency. The maximum load current is limited by the package power dissipation rating determined by the maximum junction temperature. Since the HJT is composed of a SiC JFET and a low voltage Si MOSFET, the allowable maximum junction temperature of the HJT is the same as that of SJ-MOSFETs, namely 150 °C. The experimental results show that the maximum operating current of the HJT is comparable to that of SJ-MOSs, but the EMI noise of the HJT is much suppressed due to lower dV/dt.

Abstract: The latest developments in ultra high voltage 4H-SiC IGBTs are presented. A 4H-SiC P-IGBT, with a chip size of 8.4 mm x 8.4 mm and an active area of 0.32 cm², which is double the active area of the previously reported devices [1], exhibited a blocking voltage of 15 kV, while showing a room temperature differential specific on-resistance of 41 mΩ-cm² with a gate bias of -20 V. A 4H-SiC N-IGBT with the same area showed a blocking voltage of 17 kV, and demonstrated a room temperature differential specific on-resistance of 25.6 mΩ-cm² with a gate bias of 20 V. Field-Stop buffer layer design was used to control the charge injection from the backside. A comparison between N- and P- IGBTs, and the effects of different buffer designs, are presented.

Abstract: We fabricated and characterized an ultrahigh voltage (>10kV) p-channel silicon carbide insulated gate bipolar transistor (SiC-IGBT) with high channel mobility. Higher field-effect channel mobility of 13.5 cm²/Vs was achieved by the combination of adopting an n-type base layer with a retrograde doping profile and additional wet re-oxidation annealing (wet-ROA) at 1100°C in the gate oxidation process. The on-state characteristics of the p-channel SiC-IGBT at 200°C showed the low differential specific on-resistance of 24 mΩcm² at V_G = -20 V. The forward blocking voltage of the p-channel SiC-IGBT at 25°C was 10.2 kV a the leakage current density of 1.0 μA/cm².

Abstract: We investigated the short-circuit capabilities of 1.2 kV normally-off SiC buried gate static induction transistors (SiC-BGSITs). The maximum short-circuit energy was found to be 35.6 J/cm2, which is twice that of normally-on SiC-BGSITs and 3.3–5.6 times higher than that of the Si-IGBTs. The maximum short-circuit time was 590 μs. It is concluded that these high short-circuit capabilities result from saturation characteristics of the normally-off SiC-BGSITs.