Reliability of Gate Oxides on 4H-SiC Epitaxial Surface Planarized by CMP Treatment

Abstract:

This work reports about effect of SiC epitaxial-wafer surface planarization by chemo-mechanical polishing (CMP) treatment on electrical properties of SiC-MOS capacitor. We have observed the surface morphology of 4H-SiC epitaxial layer planarized by CMP treatment using a confocal differential interference microscope, and evaluated the reliability of gate oxides on this surface using constant current time-dependent dielectric breakdown (CC-TDDB) and current-voltage (I-V) characteristics. Surface roughness such as step bunching deteriorates drastically the reliability of gate oxide, while the epitaxial-surface planarization by CMP treatment improved oxide reliability due to the high uniformity of the oxide film thickness.

• Periodical: Materials Science Forum (Volumes 778-780)
• Pages: 545-548
• DOI: https://doi.org/10.4028/www.scientific.net/MSF.778-780.545
• Online since: February 2014
• Authors: Keiichi Yamada*, Osamu Ishiyama, Kentaro Tamura, Tamotsu Yamashita, Atsushi Shimozato, Tomohisa Kato, Junji Senzaki, Hirohumi Matsuhata, Makoto Kitabatake
• Keywords: Chemo-Mechanical Polishing (CMP), Planarization, Reliability, Step Bunching, TDDB

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