Materials Science Forum Vols. 778-780

Abstract: This paper focuses on the evaluation of subsequent process steps (post-trench processes, PTPs) after 4H silicon carbide (4H-SiC) trench etching with respect to the electrical performance of trenched gate metal oxide semiconductor field effect transistors (Trench-MOSFETs). Two different types of PTP were applied after 4H-SiC trench formation, a high temperature post-trench anneal (PTA) [1] and a sacrificial oxidation (SacOx) [2]. We found significantly improved electrical properties of Planar-MOS structures using a SacOx as PTP, prior to gate oxide deposition. Besides excellent quasi-static capacitance-voltage (QSCV) behavior even at T = 250 °C, charge-to-breakdown (QBD) results up to 8.8 C/cm2 at T = 200 °C are shown to be similar on trenched surfaces as well as on untrenched surfaces of SacOx-treated Planar-MOS structures. Moreover, dielectric breakdown field strengths up to 12 MV/cm have been measured on Planar-MOS structures. However, thick bottom oxide Trench-MOS structures indicate best dielectric breakdown field strengths of 9.5 MV/cm when using a trench shape rounding PTA as the PTP.

Abstract: Despite the material advantages of Silicon-Carbide (SiC), the on resistance of 4H-SiC metal-oxide-semiconductor transistors are severely degraded by high trap densities near the oxide/SiC interface (D_it). In this work, the effect of the oxidation ambient (oxygen flow rates of 0.05 l/min-2.5 l/min) and oxidation temperature (1200°C-1600°C) on the D_it is investigated. The D_it was reduced by up to an order of magnitude using a combination of a low oxygen flow rate and a high temperature. The D_it was extracted from capacitance-voltage measurements made on MOS capacitors.

Abstract: Using Deep Level Transient Spectroscopy (DLTS) on n-type MOS capacitors we find that thermal oxidation of 4H-SiC produces deep traps at or near the SiO₂/SiC interface with two well defined DLTS peaks. The traps are located ~ 0.85 V and ~ 1.0 eV below the SiC conduction band edge and are present in wet and dry oxides as well as oxides produced by sodium enhanced oxidation and oxides grown in N₂O. The deep traps are located at the SiO/SiC interface after oxidation at 1150°C but do extend further into the SiC epilayer after oxidation at 1240°C. We identify these traps as ON1 and ON2 which been observed in epitaxial layers after oxidation at very high temperatures (1200-1500°C) [.

Abstract: This paper compares the performance of 4H-SiC MOS capacitors and MOSFETs made using the conventional NO annealing process and a high-temperature (1400°C) dry oxidation process. Through extensive C-V, G-ω, I-V and Hall measurements, the limitations of both the processes are discussed.

Abstract: The step-bunching dependence of the lifetime of metal–oxide–semiconductor capacitors on 4° off-axis 4H-SiC epitaxial wafers was investigated. The effects of the C/Si ratios in epitaxial growth and the substrate properties were examined. Step-bunching was observed at the base of triangle or trapezoid defects. Step-bunching decreased as the C/Si ratio was reduced. Time-dependent dielectric breakdown (TDDB) measurements showed that the locations of short lifetime breakdowns closely matched step-bunching positions. TDDB measurements of four different commercial substrates showed clear differences in capacitor lifetime.

Abstract: We have studied gate oxide processes for SiC trench MOSFETs. It is demonstrated that nitridation of gate oxide is effective to suppress the variation of channel mobility depending on channel plane orientation and substrate off-angles. In addition, improved channel mobility has been obtained by the combined process of NH₃ and N₂O POA.

Abstract: The electrical properties of SiO₂/4H-SiC(0001) was characterized, and it was confirmed that the NF₃ added oxidation in O₂ can achieve interface with low interface state density. Optimization of NF₃ added oxidation process was attempted to obtain films with both good interface properties and low leakage current. It was concluded that optimization of oxidation process should take account of obtaining proper balance among the rate of oxidation, which generates impurity carbon, the ability of carbon removal, and the rate of SiO₂ etching which also affects the leakage characteristics.

Abstract: This paper reports a comparative characterization of SiO₂/SiC interfaces subjected to post-oxide-deposition annealing in N₂O or POCl₃. Annealing process of the gate oxide in POCl₃ allowed to achieve a notable increase of the MOSFET channel mobility (up to 108 cm²V^-1s^-1) with respect to the N₂O annealing (about 20 cm²V^-1s^-1), accompanied by a different temperature behaviour of the electrical parameters in the two cases. Structural and compositional analyses revealed a different surface morphology of the oxide treated in POCl₃, as a consequence of the strong incorporation of phosphorous inside the SiO₂ matrix during annealing. This latter explained the instability of the electrical behaviour of MOS capacitors annealed in POCl₃.

Abstract: In an attempt to significantly reduce the amount of nitric oxide (NO), commonly used to improve the quality of gate oxides on 4H–SiC, a series of alternative gate oxidation processes using a combination of O₂ and NO gas mixtures at low partial pressures were investigated. The properties of 4H–SiC/SiO₂ interfaces on n-type MOS capacitors were examined by the measurement of accumulation conductances over a range of frequencies. Oxide integrity was evaluated by current–voltage measurements and by the extraction of the conduction band offset barrier heights through Fowler–Nordheim (F–N) analysis. A notable reduction of accumulation conductance, indicating a reduction of near-interface traps (NITs), was observed over all measured frequencies for oxidation processes containing NO with a partial-pressure of only 2%. Gate oxides grown in mixture of O₂ and NO at low-partial-pressures demonstrated a considerable improvement of dielectric properties, increasing the barrier height to near theoretical values.

Abstract: A nitride layer was formed on a SiC surface by plasma nitridation using pure nitrogen as the reaction gas at the temperature from 800°C to 1400°C. The surface was characterized by XPS. The XPS measurement showed that an oxinitride layer was formed on the SiC surface by the plasma nitridation. The high process temperature seemed to be effective to activate the niridation reaction. A SiO₂ film was deposited on the nitridation layer to form SiO₂/nitride/SiC structure. The interface state density of the SiO₂/nitride/SiC structure was lower than that of the SiO₂/SiC structure. This suggested that the nitridation was effective to improve the interface property.