Materials Science Forum Vols. 778-780

Abstract: The use of phosphorous as a passivating agent for the SiO₂/4H-SiC interface increases the field effect channel mobility of 4H-SiC MOSFET to twice the value, 30-40cm²/V-s, that is obtained with a high temperature anneal in nitric oxide (NO). A solid SiP₂O₇ planar diffusion source is used to produce P₂O₅ for the passivation of the interface. Incorporation of phosphorous into SiO₂ leads to formation of phosphosilicate glass (PSG) which is known to be a polar material causes device instability. With a new modified thin phosphorous (P) passivation process, as described in this abstract, we can improve the stability of MOSFETs significantly with mobility around 75cm²/V.s.

Abstract: TDDB for n-type 4H-SiC MOS capacitors depleted by DC bias (named as depletion-mode TDDB) has been investigated. The lifetime distribution can apparently be classified into two groups: shorter and longer t_BD. Breakdown for the shorter t_BD occurs at a point close to a threading dislocation. In contrast, the capacitors possessing longer t_BD include no dislocation. An increase in the stress temperature and/or E_OX leads to a decrease in t_BD, indicating that the breakdown is caused by gate-oxide degradation. On the other hand, the t_BD distributions acquired by accumulation-mode TDDB are relatively even, and the breakdown point is independent of dislocations. We presume that holes excited in the SiC layer by hot electrons play an important role at a threading dislocation for depletion-mode TDDB.

Abstract: Threshold voltage (V_TH) of SiC-MOSFETs on various crystal faces has been investigated systematically using the same bias-temperature-stress (BTS) conditions. In addition, dependences of gate-oxide-forming process on V_TH instability is also discussed. Nitridation treatments such as N₂O and NH₃ post-oxidation annealing (POA) are effective in stabilization of V_TH under both positive-and negative-BTS tests regardless of crystal face. On the other hand, serious V_TH instability was confirmed in MOSFETs with gate oxide by pyrogenic oxidation followed by H₂ POA.

Abstract: The 4H-SiC MOSFET electrical response to 180 keV proton radiations at three different fluences has been evaluated. For a certain dose, the devices show an apparent improvement of their electrical characteristics likely due to the N and/or H atoms diffusion inside the oxide layer. This work complete our previous studies on high energy proton irradiation, showing that the 4H-SiC MOSFET is also robust to the low energy proton radiation, when the proton implanted range is located near the MOS interface.

Abstract: In this paper we report an unexpected improvement in the SiC DMOSFET transistor characteristics after a long temperature treatment at 150 C. The evolution of the device characteristics during a TDDB stress is compared to that after an elevated temperature treatment. The improvement in characteristics after storage at high temperature is believed to be due to instabilities caused by the quality of the SiO₂/SiC interface and its large density of defects.

Abstract: Commercial SiC MOSFETs were exposed to ionizing radiation to characterize the radiation response and to compare the observed threshold voltage (V_T) instability post-radiation exposure, with the V_T instability following bias temperature stress (BTS) testing. As expected, a large number of positively charged oxide traps were present in these devices following irradiation, resulting in a significant negative V_T shift. However, the observed V_T instability following irradiation was much smaller than that for similarly processed devices exposed to a BTS. Irradiated devices subjected to unbiased thermal treatments experienced a significant annealing of trapped holes above 100 °C. However, isochronal annealing treatments did not significantly alter the number of switching oxide traps, suggesting that a large portion of the traps activated by irradiation may lie deeper within the SiO₂, beyond the tunneling distance from the SiC.

Abstract: Reliability of gate oxide for trench-gate MOSFET was improved by deposited oxide film with uniform thickness and high-temperature annealing after trench etching. Optimum wafer orientation and trench direction for the trench gate was investigated, and the gate oxide on (11-20) plane of carbon face exhibited the longest lifetime. Influences by the roughness of sidewall and the radius of trench corner are discussed.

Abstract: The impact of mobile ions intrinsically generated in thermally grown SiO₂ by high-temperature forming gas annealing (FGA) on the SiO₂/4H-SiC interface properties was studied by means of electrical characterization of SiC metal-oxide-semiconductor (MOS) capacitors. Unlike Si devices, mobile ions located at the interfaces were found to cause a remarkable stretch-out of capacitance-voltage (C-V) curve near the accumulation condition, and the degree of stretch-out was more pronounced with increasing probe frequency. This suggests that the interface states with a long emission time constant are formed near the conduction band edge due to the mobile ions. To clarify this unusual phenomenon, several characterization techniques to evaluate interface state densities (D_it), including Terman, conductance, and C-ψ_s methods, were employed. The D_it values estimated for SiO₂/SiC interfaces with mobile ions were a few times as large as those without mobile ions.

Abstract: This work reports about effect of SiC epitaxial-wafer surface planarization by chemo-mechanical polishing (CMP) treatment on electrical properties of SiC-MOS capacitor. We have observed the surface morphology of 4H-SiC epitaxial layer planarized by CMP treatment using a confocal differential interference microscope, and evaluated the reliability of gate oxides on this surface using constant current time-dependent dielectric breakdown (CC-TDDB) and current-voltage (I-V) characteristics. Surface roughness such as step bunching deteriorates drastically the reliability of gate oxide, while the epitaxial-surface planarization by CMP treatment improved oxide reliability due to the high uniformity of the oxide film thickness.

Abstract: La_xHf_yO nanolaminated thin film deposited using atomic layer deposition process has been studied as a high-K gate dielectric in 4H-SiC MOS capacitors. The electrical and nano-laminated film characteristics were studied with increasing post deposition annealing (PDA) in N₂O ambient. The result shows that high quality La_xHf_yO nano-laminated thin films with good interface and bulk qualities are fabricated using high PDA temperature.