Feasibility of SiC Threshold Voltage Drift Characterization for Reliability Assessment in Production Environments

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Abstract:

We reviewed the practical challenges of assessing the threshold voltage drift of SiC MOSFETs in the context of a commercial production environment and qualification standards. Stress bias interruption is a key challenge owing to the rapid recovery of threshold following the removal of bias and the necessity of delays and bias interruptions when qualifying device lots. The test standards in use proscribe how such interruptions should be handled using a re-application of the stress once the device is ready for characterization but these turn out to be completely inadequate when dealing with the trapping mechanics of SiC MOS. Our data indicates that a relatively short stress re-application can be successful at restoring a majority of the threshold voltage drift, scaling with the square root of the interruption time. Additionally, it is important to re-apply the stress bias even for brief interruptions since the threshold recovers so quickly (as opposed to the 96-hour stress interrupt window that is allowed before any re-application is necessary in JESD22 A-108D).

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509-512

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May 2017

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© 2017 Trans Tech Publications Ltd. All Rights Reserved

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[1] AEC-Q101 Rev-D1 Failure Mechanism Based Stress Test Qualification For Discrete Semiconductors (base document), Automotive Electronics Council, (2013).

Google Scholar

[2] D.A. Gajewski, S.H. Ryu, M. Das, B. Hull, J. Young, J.W. Palmour, Reliability Performance of 1200 V and 1700 V 4H-SiC DMOSFETs for Next Generation Power Conversion Applications, Mater. Sci. Forum. 778–780 (2014) 967–970.

DOI: 10.4028/www.scientific.net/msf.778-780.967

Google Scholar

[3] JEDEC Standard - Temperature, Bias, and Operating Life, JEDEC Solid State Technology Association, (2010).

Google Scholar

[4] R. Green, A. Lelis, D. Habersat, Threshold-voltage bias-temperature instability in commercially-available SiC MOSFETs, Jpn. J. Appl. Phys. 55 (2016) 04EA03.

DOI: 10.7567/jjap.55.04ea03

Google Scholar

[5] D.B. Habersat, A.J. Lelis, R. Green, M. El, Comparison of Test Methods for Proper Characterization of VT in SiC MOSFETs, Mater. Sci. Forum. 858 (2016) 833–839.

DOI: 10.4028/www.scientific.net/msf.858.833

Google Scholar