Investigation of Carrot Reduction Effect on 4H-Silicon Carbide Epitaxial Wafers with Optimized Buffer Layer

Yuichiro Mabuchi; Tatsuya Masuda; Daisuke Muto; Kenji Momose; Hiroshi Osawa

doi:10.4028/www.scientific.net/MSF.897.75

Paper Titles

Improvement of Quality of Thick 4H-SiC Epilayers
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Very High Sustainable Forward Current Densities on 4H-SiC p-n Junctions Formed by VLS Localized Epitaxy of Heavily Al-Doped p⁺⁺ Emitters
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V and Ti Doping in 4H-SiC Epitaxy for Reduction of Carrier Lifetimes
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Hydrogen Etching Influence on 4H-SiC Homo-Epitaxial Layer for High Power Device
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Investigation of Carrot Reduction Effect on 4H-Silicon Carbide Epitaxial Wafers with Optimized Buffer Layer
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Influence of Growth Temperature on Site Competition Effects during Chemical Vapor Deposition of 4H-SiC Layers
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Depth Profile of Doping Concentration in Thick (> 100 μm) and Low-Doped (< 4 × 10¹⁴ cm^-3) 4H-SiC Epilayers
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Silicon Deposition on 3C-SiC Seeds of Different Orientations
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Growth of Cubic Silicon Carbide on Silicon Using Hot Filament CVD
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HomeMaterials Science ForumMaterials Science Forum Vol. 897Investigation of Carrot Reduction Effect on...

Investigation of Carrot Reduction Effect on 4H-Silicon Carbide Epitaxial Wafers with Optimized Buffer Layer

Abstract:

We investigated the carrot-defect reduction effect by optimizing the buffer layers of 4H-Silion Carbide (SiC) epitaxial wafers. The SiC epitaxial wafer with the 0.5 μm-thick optimized condition-B buffer layer show the carrot-defect density of 0.13 cm^-2, since that with the conventional-A buffer layer were 0.68 cm^-2. Although the average bunching length with the optimized condition-B buffer layer was 7-times longer than those with the conventional condition-A buffer layer, we could reduce the bunching length by applying the optimized condition-B only to the initial 0.05 μm-thick buffer layer. Finally, with the initial 0.05 μm-thick optimized condition-B buffer layers, we could achieve the SiC epitaxial wafers with only half the carrot-defect densities of those with the conventional condition-A buffer layers, while the average bunching lengths were less than 100 μm. With this condition, we could achieve the estimated yield of 90.1% with 4 x 4 mm chips, while that with the conventional condition-A buffer layer was 81.9%.

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Periodical:

Materials Science Forum (Volume 897)

Pages:

75-78

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.897.75

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Online since:

May 2017

Authors:

Yuichiro Mabuchi*, Tatsuya Masuda, Daisuke Muto, Kenji Momose, Hiroshi Osawa

Keywords:

4H-SiC Epitaxial Growth, Buffer Layer, Bunching, Carrot Defect, MOSFET, Surface Defect, Surface Morphology

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