Suppression of PBTI of SiC-MOSFETs under 100 kHz Gate-Switching Operation by Using a Gate Off-Voltage of -5 V

Eiichi Murakami; Takahiro Furuichi; Tatsuya Takeshita; Kazuhiro Oda

doi:10.4028/www.scientific.net/MSF.924.711

Paper Titles

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4H-SiC Trench MOSFET with Ultra-Low On-Resistance by Using Miniaturization Technology
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Suppression of PBTI of SiC-MOSFETs under 100 kHz Gate-Switching Operation by Using a Gate Off-Voltage of -5 V
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Short-Circuit Robustness of SiC Trench MOSFETs
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HomeMaterials Science ForumMaterials Science Forum Vol. 924Suppression of PBTI of SiC-MOSFETs under 100 kHz...

Suppression of PBTI of SiC-MOSFETs under 100 kHz Gate-Switching Operation by Using a Gate Off-Voltage of -5 V

Abstract:

Positive bias temperature instability (PBTI) is one of the crucial issues in SiC-MOSFETs’ introduction to automotive applications. We have investigated PBTI of commercially available SiC-MOSFETs under gate-switching operation to consider real power circuits operation. The use of negative gate off-voltage (V_gs(OFF)~-5 V) is shown to suppress V_th shift (ΔV_th) under 100 kHz gate-switching operation. This gate voltage corresponds to the flat band condition, under which the electrons trapped by the near-interfacial traps are effectively detrapped through the interface states around the conduction band edge.

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Periodical:

Materials Science Forum (Volume 924)

Pages:

711-714

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.924.711

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Online since:

June 2018

Authors:

Eiichi Murakami*, Takahiro Furuichi, Tatsuya Takeshita, Kazuhiro Oda

Keywords:

Interface States, Near-Interfacial Trap, PBTI, Reliability, SiC-MOSFET

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