Low-Parasitic-Capacitance Self-Aligned 4H-SiC nMOSFETs for Harsh Environment Electronics

Abstract:

Article Preview

Low-parasitic-capacitance 4H-SiC nMOSFETs using a novel self-aligned process were suggested and demonstrated. In these nMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain, drain-source capacitance) were investigated and low parasitic capacitance was achieved by the self-aligned structure.

Info:

Periodical:

Edited by:

Robert Stahlbush, Philip Neudeck, Anup Bhalla, Robert P. Devaty, Michael Dudley and Aivars Lelis

Pages:

971-974

Citation:

T. Kurose et al., "Low-Parasitic-Capacitance Self-Aligned 4H-SiC nMOSFETs for Harsh Environment Electronics", Materials Science Forum, Vol. 924, pp. 971-974, 2018

Online since:

June 2018

Export:

Price:

$38.00

* - Corresponding Author

[1] L. Lanni, B. G. Malm, M. Östling, and C.-M. Zetterling, IEEE Electron Device Lett., 34(9) (2013) 1091-1093.

DOI: https://doi.org/10.1109/led.2013.2272649

[2] D. J. Spry, P. G. Neudeck, L. Chen, D. Lukco, C. W. Chang, G. M. Beheim, M. J. Krasowski, and N. F. Prokop, Mat. Sci. Forum, Vol. 858, pp.908-912 (2016).

DOI: https://doi.org/10.4028/www.scientific.net/msf.858.908

[3] H. Nagatsuma, S-I. Kuroki, M. De Silva, S. Ishikawa, T. Maeda, H. Sezaki, T. Kikkawa, M.Ostling, and C.-M. Zetterling, Mat. Sci. Forum, Vol. 858, pp.573-576 (2016).

DOI: https://doi.org/10.4028/www.scientific.net/msf.858.573

[4] S-I. Kuroki, H. Nagatsuma, M. De Silva, S. Ishikawa, T. Maeda, H. Sezaki, T. Kikkawa, T.Makino, T. Ohshima, M. Ostling, and C.-M. Zetterling, Mat. Sci. Forum, Vol. 858, pp.864-867 (2016).

DOI: https://doi.org/10.4028/www.scientific.net/msf.858.864

[5] G. Liu, Y. Xu, C. Xu, A. Basile, F. Wang, S. Dhar, E. Conrad, P. Mooney, T. Gustafsson, L. C. Feldman, Applied Surface Science, 324 30-34 (2015).

Fetching data from Crossref.
This may take some time to load.