Low-Parasitic-Capacitance Self-Aligned 4H-SiC nMOSFETs for Harsh Environment Electronics
Low-parasitic-capacitance 4H-SiC nMOSFETs using a novel self-aligned process were suggested and demonstrated. In these nMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain, drain-source capacitance) were investigated and low parasitic capacitance was achieved by the self-aligned structure.
Robert Stahlbush, Philip Neudeck, Anup Bhalla, Robert P. Devaty, Michael Dudley and Aivars Lelis
T. Kurose et al., "Low-Parasitic-Capacitance Self-Aligned 4H-SiC nMOSFETs for Harsh Environment Electronics", Materials Science Forum, Vol. 924, pp. 971-974, 2018