Materials Science Forum Vol. 924

Abstract: We investigated the relationship between ion implantation-induced defects and electrical characteristics, especially focusing on the leak failure rate in SiC IEMOSs and PN diodes. It was found that dislocation exists in each leakage point by analyzing identical leak-failed IEMOS by emission microscopy and refraction X-ray topography. The leak failure rate of the PN diodes and IEMOS was improved with an increase in the ion implantation temperature under the implantation and annealing conditions used in this experiment. It is considered that ion implantation-induced defects lead to an increase in leak failure rates, and also enable a decrease in leak failure rates by raising the implantation temperature up to 600 deg.C.

Abstract: Thermal annealing plays a crucial role for healing the defectiveness in the ion implanted regions of DIMOSFETs (Double Implanted MOSFETs) devices. In this work, we have studied the effect of a double step annealing on the body (Al implanted) and the source (P implanted) regions of such devices. We found that a high temperature annealing (1750°C, 1h) followed by a lower temperature one (1500°C, 4h) is mandatory to achieve low defects concentration and good crystal quality in both the n-and p-type zones of the device.

Abstract: This paper presents the analysis of Aluminum profile implanted into 4H-SiC with low background doping concentration. A strong lateral straggling effect was discovered with secondary electron potential contrast (SEPC) method, and analyzed by Sentaurus Monto Carlo simulations. The effect of lateral straggling was included in the edge termination design using Sentaurus TCAD simulation tool, and the results are compared with design not including the lateral straggling effect. The effect of interface charge on the electric field distribution and breakdown voltage of different 10 kV device edge termination designs was compared and analyzed.

Abstract: We investigated process induced defects at various ion implantation conditions, and evaluated forward voltage degradation of body diode in 3.3 kV SiC MOSFET. First, by using photoluminescence (PL) observation, we evaluated the formation level of Basal Plane Dislocations (BPD) induced by Al implantation and anneal process with various Al implantation dose. Second, 3.3 kV double-diffused SiC MOSFETs were fabricated and forward current stress tests were performed to body diodes in SiC MOSFETs. Then, electrical characteristics of SiC MOSFETs before and after the stress test were measured, and expanded Stacking faults (SFs) in SiC epitaxial layer after the stress test were observed by PL imaging method. These results indicate that low dose or high temperature Al implantation conditions can suppress the formation of BPDs, and SiC MOSFETs fabricated using optimized Al implantation conditions show high reliability under current stress test.

Abstract: In order to develop the high etching rate reactor for silicon carbide, the 50-mm-diameter C-face 4H-silicon carbide wafer was etched using the chlorine trifluoride gas at 500 °C. By the deep etching, the concentric-circle-shaped valleys were formed at the positions corresponding to the radii of the pin-hole arrays of the gas distributor, as predicted by the calculation. The etching rate profile of 4H-silicon carbide was concluded to have a relationship with the local chlorine trifluoride gas supply . The wafer bow was small, even the wafer was very thin, about 160 μm thick.

Abstract: The stability/ erosion of the interface between a C-cap and 4H-SiC have been studied by secondary ion mass spectrometry (SIMS). Aluminum implantation has been used to monitor the position of the moving interface as well as to investigate the influence on the interface stability by the crystal quality of the 4H-SiC. After Al implantation a C-cap has been deposited by pyrolysis of photoresist. Subsequent annealing has been performed at 1900 and 2000 °C with durations between 15 minutes and 1 hour. SIMS measurements have been performed without removal of the C-cap. The surface remains smooth after the heat treatment, but a large amount of SiC material from the uppermost part of the wafer is lost. The amount of lost material is related to for instance annealing temperature, ambient conditions and ion induced crystal damage. This contribution gives a brief account of the processes governing the SiC surface decomposition during C-cap post implant annealing.

Abstract: This work reports on the electrical and microstructural properties of Ti/Al/Ni contacts to p-type implanted 4H-SiC obtained by rapid thermal annealing of a metal stack of Ti (70 nm)/Al (200 nm)/Ni (50 nm). The contact characteristics were monitored at increasing value of the annealing temperature. The Ohmic behavior of the contact, with a specific contact resistance value of 2.3×10^-4 Ω·cm², is obtained for an annealing at 950 °C. The structural analyses of the contact, carried out by XRD and TEM, reveal the occurrence of reactions, with the detection of the Al₃Ni₂ and AlTi phases in the upper part of the contact and of an epitaxially oriented TiC layer at the interface. These reactions are considered the key factors in the formation of an Ohmic contact in our annealed Ti/Al/Ni system. The temperature-dependence study of the electrical characteristics reveals a predominant thermionic field emission (TFE) mechanism for the current conduction through the contact, with a barrier height of 0.56 eV.

Abstract: We report the initial results of using co-sputtered Pt:Ti 80:20 at. % composition ratio metallization as a diffusion barrier against gold (Au) and oxygen (O), as an interconnect layer, as well as forming simultaneous ohmic contacts to n-and p-type 4H-SiC. Having a single conductor with such combined multi-functional attributes would appreciably reduce the fabrication costs, processing time and complexity that are inherent in the production of SiC based devices. Auger Electron Spectroscopy, Focused Ion Beam-assisted Field Emission Scanning Electron Microscopy and Energy Dispersive Spectroscopy analyses revealed no Au and O migration to the SiC contact surface and minimal diffusion through the Pt:Ti barrier layer after 15 minutes of exposure at 800 oC in atmosphere, thus offering potential long term stability of the ohmic contacts. Specific contact resistance values of 7 x 10^-5 and 7.4 x 10^-4 Ω-cm² were obtained on the n (N_d=7 x 10¹⁸ cm^-3) and p (N_a=2 x 10²⁰ cm^-3) -type 4H-SiC, respectively. The resistivity of 75 μΩ-cm was obtained for the Pt:Ti layer that was sandwiched between two SiO₂ layers and annealed in pure O ambient up to 900 °C, which offers promise as a high temperature interconnect metallization.

Abstract: This study shows that a thin Ni film on Al/Ti/4H-SiC metal pads allows to preserve the pad form factor during a 1000 °C/2 min treatment, provided that the Al and Ti film thicknesses are sufficiently thin. Moreover, by reducing the Al to Ti thickness ratio, droplet formation in the contact area is avoided and a mirror-like appearance is obtained. This optimal contact morphology corresponds to a specific contact resistance of few 10^-4 Ωcm² at room temperature on p-type 4H-SiC with resistivity in the range 0.1 – 1 Ωcm.

Abstract: Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10^-4 Ω cm²) to epitaxially grown p-type (>5×10¹⁸ cm^-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni₂Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.