Materials Science Forum Vol. 924

Abstract: The effect of local lifetime control by proton irradiation on the OCVD response of a 10 kV SiC PiN diode was investigated. Carrier lifetime was reduced locally by irradiation with 800 keV protons at fluences up to 1x10¹¹ cm^-2. Radiation defects were characterized by DLTS and C-V profiling; excess carrier dynamics were measured by the OCVD and analyzed using the calibrated device simulator ATLAS from Silvaco, Inc. Results show that proton implantation followed by low temperature annealing can be used for controllable local lifetime reduction in SiC devices. The dominant recombination centre is the Z_1/2 defect, whose distribution can be set by irradiation energy and fluence. The local lifetime reduction, which improves diode recovery, can be monitored by OCVD response and simulated using the SRH model accounting for the Z_1/2 defect.

Abstract: In this paper, the application of a high temperature thermal oxidation and annealing process to 4H-SiC PiN diodes with 35 μm thick drift regions is explored, the aim of which was to increase the carrier lifetime in the 4H-SiC. Diodes were fabricated using 4H-SiC material and underwent a thermal oxidation in dry pure O₂ at 1550^◦C followed by an argon anneal at the same temperature. Reverse recovery tests indicated a carrier lifetime increase of around 42% which is due to increase of excessive minority carriers in the drift region. The switching results illustrate that the use of this process is a highly effective and efficient way of enhancing the electrical characteristics of high voltage 4H-SiC bipolar devices.

Abstract: In this work, we examined the oxidation growth rates of the (0001) Si-face and (11−20) a-faces of 4H-SiC by carrying out oxidation in the 850°C-950 °C temperature range in a plasma afterglow furnace for application to trench MOSFETs. At 900 °C, this method results in almost equal oxide thickness on the Si-face and a-face which would nominally correspond to trench bottom and sidewalls in trench devices. Our results indicate that after NO annealing, the electronic properties of the plasma oxidized SiO₂/SiC interface is comparable to control samples with gate oxides formed by dry oxidation at 1150 °C followed by NO annealing. Next, the effect of reactive ion etching (RIE) of 4H-SiC surfaces prior to gate oxidation was investigated using planar 4H-SiC MOS capacitors. Our experiments show that oxidation followed by NO annealing of surfaces with smooth morphology following the RIE step, results in similar interface charge and trap densities as MOS capacitors which did not undergo the RIE etching.

Abstract: The characteristics of near interface electron and hole traps in n-type 4H-SiC MOS capacitors with and without nitric oxide (NO) passivation have been systematically investigated. The hysteresis of the bidirectional capacitance-voltage (C-V) and the shift of flat band voltage (V_fb) caused by bias stress (BS) with and without ultraviolet light (UVL) irradiation are used for studying the influence of near interface electron traps (NIETs) and near interface hole traps (NIHTs). Compared with Ar annealed process, NO passivation can effectively reduce the density of NIETs, but induce excess NIHTs in the SiC MOS devices. What’s worse is that part of the trapped hole cannot be released easily from the NIHTs in the NO annealed sample, which may act as the positive fixed charge and induce the negative shift of threshold voltage.

Abstract: For the improvement of a SiC/SiO₂ interface of SiC-MOSFET, we examined O₂ partial pressure (PO₂) controlled (OPC) oxidation process for the gate oxide formation. The OPC oxidation process has a potential to reduce interface state density (D_it) at SiC/SiO₂ interface by using appropriate PO₂ and oxidation temperature. However the process requires rapid thermal annealing which is not suitable for mass production. Thus we investigated the process using furnace. First, we optimized the OPC oxidation process for the furnace to realize low interface defect density. Secondly, we confirmed that reduction of D_it was determined by desorption of excess carbon in OPC process by the C–ψs measurement and X-ray photoelectron spectroscopy. Finally, a DMOSFET was fabricated using optimized OPC process. We measured the transfer characteristics, and found that the drain current with OPC was larger than without OPC process.

Abstract: The gate insulator process for SiC-MOSFET was examined and high-quality interface was realized by employing the pre-annealing process before high-temperature N₂ annealing. The pre-annealing evidently activated the interface to introduce nitrogen, and then field-effect mobility exceeded 50 cm²/Vs. The fabricated sample also demonstrated superior bias temperature instability (BTI) and excellent breakdown electric field of 11.7 MV/cm.

Abstract: We investigated the impact of high-temperature H₂/Ar mixture gas treatment of 4H-SiC(0001) surfaces before SiO₂ deposition on the electrical properties of SiO₂/SiC interfaces. Physical characterizations revealed that the SiC surface treated by the H₂/Ar mixture gas exhibited a (√3×√3)R30° structure composed of Si-O bonds, indicating that a well-ordered and stable silicate adlayer was formed by the treatment to passivate SiC(0001) surface. Electrical defects at the CVD-grown SiO₂/SiC interface was significantly reduced by the treatment. Consequently, a peak electron mobility in SiC-MOSFETs with the deposited gate oxides was enhanced to 24.9 cm²/Vs.

Abstract: Effects of CF₄ etching on 4H-SiC MOS capacitor were investigated. Fluorine atoms were introduced to surface of 4H-SiC using CF₄ dry etching process as a surface treatment, and 4H-SiC MOS capacitors with dry-oxide were fabricated with this treatment. As the results, breakdown electric field of the MOS capacitors was increased and variation of the characteristics became lower than that of MOS capacitor without this treatment.

Abstract: In this work, we study the effects of NO anneals on the interface of 4H-SiC MOSFETs via spin dependent charge pumping, an electrically detected magnetic resonance technique. We make measurements at high and ultra-low resonance frequencies. Our results indicate that the NO anneals both change the silicon vacancy energy levels as well as induces disorder at the interface. In addition, our results indicate that the changes in energy levels involve N atoms very close to V_Si sites.

Abstract: We present a temperature-dependence electrical characterization of the oxide/semiconductor interface in MOS capacitors with a SiO₂ layer deposited on 4H-SiC using dichlorosilane and nitrogen-based vapor precursors. The post deposition annealing process in N₂O allowed to achieve an interface state density D_it  9.0×10¹¹cm^-2eV^-1 below the conduction band edge. At room temperature, an electron barrier height (conduction band offset) of 2.8 eV was measured using the standard Fowler-Nordheim tunneling model. The electron conduction through the SiO₂ insulating layer was evaluated by studying the experimental temperature dependence of the gate current. In particular, the Fowler-Nordheim electron barrier height showed a negative temperature coefficient (dφ_B/dT = - 0.98 meV/°C), which is very close to the expected value for an ideal SiO₂/4H-SiC system. This result, obtained for deposited SiO₂ layers, is an improvement compared to the values of the temperature coefficient of the Fowler-Nordheim electron barrier height reported for thermally grown SiO₂. In fact, the smaller dependence of φ_B on the temperature observed in this work represents a clear advantage of our deposited SiO₂ for the operation of MOSFET devices at high temperatures.