Materials Science Forum Vol. 924

Abstract: PowerAmerica sponsored the development by NCSU of a process for manufacturing power MOSFETs and JBS Rectifiers in 2015. This process, named PRESiCE^TM, was successful in making 1.2 kV rated state-of-the-art 4H-SiC power devices (MOSFETs, BiDFETs, and JBS Rectifiers) in the X-Fab foundry. In addition, we were successful in monolithically integrating a JBS fly-back rectifier into the power MOSFET structure to create the power JBSFET which allows saving significant (~ 40 %) chip area and reducing package count in half. In the second year (2016), NCSU has qualified the process for manufacturing these power devices at X-Fab.

Abstract: We have developed a process that is able to detect, count, and map micropipes on SiC substrates. This process uses a polarized light microscope to scan the wafer. The pictures taken are analyzed with a program that produces a micropipe map as well as numerical defect distribution data in a text file. The results of the process were validated with x-ray topography measurement. The repeatability of this process is also studied and reported.

Abstract: The dislocation analysis of latent scratch induced chemical mechanical polishing process on 4H-silicon carbide (SiC) using the multi directional scanning transmission electron microscopy (STEM) method and elastic stain measurement were performed. A scanning electron microscope image shows that a latent scratch extended toward the [30] direction and the width is about 50 nm. Cross sectional STEM images shows that the depth of latent scratch due to distortion is about 20 nm. From the result of plan view STEM observation along [000] direction, it was observed that a latent scratch had two defect lines toward the [30] direction, which were a loop type on upper side and a linear type on the lower side. The Burgers vector of each defect have a component in basal plane. Elastic strain mapping was performed using transmission electron microscope equipped with a procession diffraction system. Inside the latent scratch indicates stain-free field, however around latent scratch indicates compressive strain field. About 1.5 % compressive strain field x, y direction and shear strain along latent scratch exists on typical area. As a results of STEM and elastic strain analysis, the atomic arrangement in basal plane seems to be related with the compressive strain around latent scratch.

Abstract: In this work a comparison between different 6 inches 4H-SiC commercial substrates after post processing has been shown. The main comparison was done between two different suppliers after a thinning process that leaves the sample with a final thickness of 150 microns. After the processing the two substrates show different behavior with different curvature and residual stress. X-Ray diffraction show different crystal quality and curvature values of the substrates. Micro-Raman show different residual stress of the substrates before and after the thinning process. Moreover, molten KOH etching for dislocation detection also show different value of dislocation density for both substrates.

Abstract: Processing silicon carbide (SiC) wafers to achieve an epi-ready quality finish typically requires many lapping and a very long chemical mechanical polishing (CMP) steps. In this paper, we report the thinning down of 6” SiC wafers to sub-nanometer surface finish in less than two hours. Three process steps (rough grinding, nanogrinding and CMP) are involved. Rough grinding thins down the wafer with fast feed rate and maintain excellent flatness. Nanogrinding allows the surface finish to improve down to a few nanometers. The last CMP step provides high planarization efficiency. Overall the throughput of SiC processing is substantially increased over current market solutions.

Abstract: A latent scratch which is an extremely shallow scratch induced on a SiC wafer during chemo-mechanical polishing (CMP) has been investigate by mirror projection electron microscopy (MPJ), low-energy scanning electron microscopy (LESEM), atomic force microscopy (AFM) and scanning transmission electron microscopy (STEM). The latent scratch, which is difficult to detect by using optical microscopes, was easily visualized by MPJ as a high contrast dark line. The morphology of detected latent scratch is less than 1nm in depth and about 30nm in full width at half depth by AFM evaluation. The STEM observation revealed the latent scratch was accompanied two dislocation arrays. One contains loop-like dislocations and the other contains spiky dislocations, both lying in the wafer at a few ten nm in depth.

Abstract: With the gaining demand for SiC semiconductor devices it is more and more challenging to meet the requirements for SiC volume production with the state of the art wafer dicing technology. In order to overcome this challenge the laser based dicing technology Thermal Laser Separation (TLS-Dicing^TM) was assessed for SiC volume production within the European project SEA4KET. This paper presents the key results of this project. It could be demonstrated that the demand of SiC volume production regarding throughput and cost as well as edge quality and electrical performance of diced chips can be met with TLS-Dicing^TM.

Abstract: High-energy neutrons produced by cosmic ray interactions with our atmosphere are known to cause single-event burnout (SEB) failure in power devices operating at high fields. We have performed accelerated high-energy neutron SEB testing of SiC and Si power devices at the Los Alamos Neutron Science Center (LANCSE). Comparing Wolfspeed SiC MOSFETs having different voltage (900V – 3300V) and current (3.5A – 72A) ratings, we find a universal behavior when scaling failure rates by active area, and scaling drain bias by avalanche voltage. Moreover, diodes and MOSFETs behave similarly, revealing that the SiC drift dominates the failure characteristics for both device types. This universal scaling holds for SiC MOSFETs from other manufacturers as well. The SEB characteristics of Si power IGBT and MOSFET devices show that near their rated voltages failure rates of Si devices can be 10X higher than that of comparable SiC MOSFET devices. Thus, Si devices are more susceptible to SEB failure from voltage overshoot conditions.

Abstract: In the ideal case, superjunction (SJ) drift regions theoretically exhibit a linear relationship between specific-on resistance R_on,sp and blocking voltage V_BR, but this requires perfect charge balance between the alternating n and p pillars. If any degree of imbalance exists, the relationship becomes quadratic, similar to a conventional drift region, although with somewhat improved performance. In this work, we analyze superjunction drift regions in 4H-SiC under realistic degrees of charge imbalance and show that, with proper design, a reduction in specific on-resistance of 2~10x is possible as long as the imbalance remains less than ±20%.

Abstract: Implantation-free mesa etched ultra-high-voltage 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. The diode’s design allows a high breakdown voltage of about 19.3 kV according to simulations. No reverse breakdown is observed up to 13 kV with a very low leakage current of 0.1 μA. A forward voltage drop (V_F) and differential on-resistance (Diff. R_on) of 9.1 V and 41.4 mΩ cm² are measured at 100 A/cm², respectively, indicating the effect of conductivity modulation.