Materials Science Forum Vol. 924

Abstract: This paper presents the design and fabrication of 1200V-rated SiC JBS diodes in a manufacturing environment. Various designs of p⁺-grids and edge termination structures were proposed and fabricated on 6-inch SiC substrates. Experimental results show that deeper p⁺ n junctions are necessary to reduce the leakage current in blocking mode of operation. It was also demonstrated that the hybrid-JTE edge termination structure is very efficient to provide a near-ideal breakdown voltage. Ti and Ni Schottky metals were compared with respect to forward voltage drops and reverse blocking behaviors at high temperatures up to 200 °C.

Abstract: Modeling and simulation of 3C-SiC power devices such as MOSFETs and diodes requires a model for the breakdown field that is consistent with the Monte-Carlo-simulated ionization rates of electron and holes and supported by experimental results. The challenge one faces is the limited number of publications reporting such calculations and the limited availability of high-quality ionization breakdown data for 3C-SiC diodes. We therefore performed a series of 2D simulations of both n-type and p-type Schottky diodes and p⁺-n diodes that confirms the general breakdown field trend with doping density obtained from experiments. We uncovered a difference between n-type and p-type diode breakdown behavior, identified the discrepancy between the calculations and the experimental data, and extracted a simple breakdown field model, useful for further 3C-SiC device design and simulation.

Abstract: Silicon Carbide JBS diodes are capable, in forward bias, of carrying surge current of magnitude significantly higher than their rated current, for short periods. In this work, we examine the mechanisms of device failure due to excess surge current by analyzing variation of failure current with device current and voltage ratings, as well as duration of current surge. Physical failure analysis is carried out to correlate to electrical failure signature. We also quantify the impact, on surge current capability, of the resistance of the anode ohmic contact to the p-shielding region.

Abstract: This paper proposes a novel high-gain 4H-SiC BJT structure with a p-type epitaxial layer on top of the extrinsic base layer. The current gain of the novel structure is improved by 140% compared with the conventional one by the simulator tool with the number of reasonable interface traps, which could be ascribed to the epitaxial layer to reduce the surface recombination in the extrinsic base. The process to fabricate this structure is also proposed in the paper.

Abstract: Effects of a parasitic region in SiC BJTs on conductivity modulation and a forced current gain (β_F) were investigated by using TCAD simulation with various device structures. By introducing an Al⁺-implanted region below the base parasitic region, β_F can be improved because the implanted region can reduce the base spreading resistance, leading to alleviation of debiasing effect. β_F in devices with various parasitic areas, whose base spreading resistances were reduced by the Al⁺-implantation, were compared. We found that β_F can be enhanced by expanding the parasitic area if the base spreading resistance is sufficiently reduced. The higher β_F is attributed to an expanded conductivity-modulated region. The collector current spreading in the collector layer and the hole injection from the parasitic region as well as from the intrinsic region can play a role to evoke the conductivity modulation. Thus, the larger parasitic region can expand the conductivity-modulated region, resulting in expansion of an active area and the enhancement of β_F.

Abstract: An investigation into the increased leakage currents and reduced blocking voltages associated with 1450°C lifetime enhancement oxidation for the 4H-SiC p-GTOs is presented. Roughening of the 4H-SiC surface due to localized crystallization of SiO₂, or crystobalite formation, during the high temperature oxidation was identified as one of the main causes of this issue. A factor of 30 difference in permeability to O₂ between amorphous SiO₂ and crystobalite caused uneven oxidation, which resulted in significant roughness. This roughness, placed at the metallurgical junction between the gate and the drift layer, where the E-field is greatest, is believed to be responsible for the premature breakdown characteristics. A 2-step lifetime enhancement process, which moves this roughness to the lower E-field region of the device was introduced to alleviate this issue. A 15 kV 4H-SiC p-GTO with the 2-step lifetime enhancement process demonstrated a significant reduction in V_F over the 1300°C oxidized devices, without any impact on blocking characteristics.

Abstract: A box cell layout and a hole-barrier structure were used to realize low-on-voltage n-channel 4H-SiC IGBTs with 6.5-kV blocking capability. Box cell layout can increase the channel width, leading to reduction of the channel resistance and an enhancement of electron injection from an emitter. Hole-barrier structure, which is a potential barrier for holes to prevent them from flowing out of the emitter, can enhance conductivity modulation. An on-voltage of 3.98 V at a collector current of 100 A/cm² was achieved from a fabricated SiC IGBTin this study. Since the on-voltage of a SiC IGBT with a conventional structure was 4.81 V at the same collector current, the effect of our new structure was successfully shown to reduce the on-voltage of SiC IGBTs. An estimation of each voltage component involved in the on-voltage was also carried out by utilizing a device simulation, and the estimation shows that a SiC IGBT incorporating a box layout and hole-barrier structure will thus have quite a low drift-layer voltage and an on-voltage close to the limit determined by the bipolar built-in voltage.

Abstract: Wide bandgap semiconductors, such as 4H SiC, are suitable for power regulating devices, due to compatibility with conventional process integration, high breakdown voltage and thermal conductivity [1]. For RF applications, in order to achieve better switching speed, high cut off frequency, and low series resistance (Rdson), it is essential to choose the right gate metals [2]. Engineering of the gate metals not only improves the critical device parameters by adjustment of the metal workfunction, but also affects how the high aspect ratio trenches are filled for a next generation SIT device configuration [3] - [5].

Abstract: This paper proposes a new N-type 4H-SiC extraction-enhanced vertical insulated-gate bipolar transistor (E²VIGBT), which uses a partial Schottky contact to the collector region bottom surface as a carrier extractor to enhance the carrier extraction, so that the switching performance will be improved. TCAD simulation shows that, at an operation frequency of 250 kHz, the E²VIGBT offers a turn-off loss decrease of 69.2% and a total energy loss in a single period reduction of 34.4% when compared with conventional field-stop 4H-SiC IGBTs. With further specific optimization, the proposed structure consumes less energy in a much wider frequency range. The simulation results indicate that this new type of IGBT performs better in high frequency applications.

Abstract: This paper presents and discusses the depletion mechanisms that dominate in a TSI-VJFET under different bias conditions as expressed by the gate-source (C_GS) and gate-drain (C_GD) capacitances. It is shown that at pinch off the dominant capacitance is the drift capacitance and that in conduction the drain source voltage plays a significant role in channel’s formation. Furthermore a semi empirical capacitance model is introduced. C_GS and C_GD are modeled below and above threshold voltage by considering parallel plate capacitors with different plate configuration in te two cases. Then, the derived expressions are unified using a transition function that preserves the continuity of the model. The model was adjusted and fitted adequately to measured CV data from fabricated TSI-VJFET.