Materials Science Forum Vol. 924

Abstract: Wide bandgap materials such as Silicon Carbide (SiC) has enabled the use of medium voltage unipolar devices like Metal-Oxide Field Effect Transistors (MOSFETs) and Junction Field Effect Transistors (JFETs), which can switch at much higher frequencies as compared to their silicon counterparts. It is therefore imperative to evaluate the performance of these medium voltage devices. In this paper, the static characterization and the switching performance of the new single die 3.3 kV, 45 A 4H-SiC MOSFET developed by Cree Inc are presented. The switching performance is measured through the conventional Double Pulse Test. Testing is done at a dc-link voltage of 1.5 kV for different values of current, and gate resistances.

Abstract: For the paper, we studied how bias stress interruption and reapplication influences threshold voltage (V_T) drift results in SiC DMOSFETs during 175°C bias-temperature instability (BTI) tests. Bias interruptions of even short durations were found to result in significant loss of observed V_T drift, although reapplying the stress bias for a short time immediately before making the post-stress measurement resulted in a significant recovery of the lost drift. The fractional V_T drift (i.e., the ratio of “observed” to “actual” drift) was found to behave similarly to the case of 25°C bias stressing, with an apparent empirical relationship relating to the square of the reapply time, divided by interrupt time. Although questions of bias-stressing at high temperature with room-temperature measurement remain unresolved for now, these results continue to support the feasibility of stress bias reapplication to counteract the loss in V_T drift due to delays or interruptions between stressing and measurement (which are a practical limitation imposed by the necessities of batch testing for qualification in a production environment).

Abstract: The effect of a gate trench bottom p⁺ region (BPR) on the dynamic characteristics of 4H-SiC double-trench MOSFETs was investigated. Although employing a BPR led to an improved trade-off in the static characteristics, a BPR adversely affected the switching characteristics in spite of a reduction in the Miller capacitance compared to the case without a BPR_. Simulation analysis revealed that a resistance between a BPR and a source electrode led to an increase in the switching loss. We have found reduction of the resistance is insufficient in order to provide benefits from the BPR. Hence, it is necessary to improve layouts of contacts of the BPR to the source electrode.

Abstract: Silicon carbide (SiC) trench MOSFETs, or UMOSFETs, generally exhibit lower specific on-resistance than planar DMOSFETs due to a more compact unit cell, higher electron mobility on the a-face surface, and the absence of a JFET region. In this paper we compare the performance of two types of trench UMOSFETs based on 2-D Sentaurus^TM Device simulations, and show that the single-trench oxide-protected structure exhibits ~40% lower specific on-resistance and half the peak oxide field of the double-trench design when both are optimized for maximum figure of merit.

Abstract: 1200V SiC power MOSFETs of various cell geometries are modeled in Synopsis Inc. Sentaurus TCAD. The impact of cell geometry on switching loss is studied by comparing the turn-on and turn-off losses using refined calculation methods. Under optimum circuit conditions, two different novel unit cell designs each achieve lower switching losses than conventional designs. For all the designs, lossless turn-on is impossible but lossless turn-off is achievable under circuit and biasing conditions that produce sufficiently rapid gate slew.

Abstract: An optimized layout for a trench-gate SiC-MOSFET with a self-aligned Bottom P-Well (BPW) was investigated for reduction of the specific on-resistance and switching loss. The static and dynamic characteristics of trench-gate MOSFETs with lattice and stripe in-plane structures were evaluated by varying the distance between neighboring BPWs (d_BPWs). For the stripe structure, more significant improvements on the specific on-resistance (R_on,sp), gate-source threshold voltage (V_th) were achieved compared with the lattice structure, which was found to be due to the difference in the spread of the depletion layer and the channel planes in the device.

Abstract: A shielded gate trench silicon carbide (SiC) metal oxide semiconductor field effect transistor (SG-TMOS) is proposed and investigated by simulation in this paper. The impact of shielded gate design in SG-TMOS on Miller charge (Q_gd) as well as conduction resistance (R_on) are comprehensively discussed, showing a tradeoff between Q_gd and R_on. Furthermore, the Huang’s Figure of Merit (HFOM) of the SG-TMOS with reasonable design of SG is reduced more than 20%, compared with the conventional trench MOSFET (C-TMOS). Therefore, the proposed SG-TMOS is a competitive next generation device structure for ultra-high switching speed SiC MOSFET.

Abstract: To address stringent performance and reliability requirements of industrial and traction power conversion systems we have developed planar 3,300V MOSFETs at a 6-inch SiC-compatible silicon CMOS foundry. By optimizing the unit cell structure and using a deep current-spreading layer we demonstrated a low MOSFET specific on-resistance R_DSA=11.2 mΩ·cm² (I_D=5A, V_GS=15V) and fast switching for the baseline design. Robust short-circuit handling (7.5μs at Vds=1500V and 5.0μs at Vds=2200V) was demonstrated with an alternative unit cell design with R_DSA=14.8 mΩ·cm² (I_D=5A, V_GS=15V).

Abstract: A comprehensive comparison of 3C-SiC and 4H-SiC power MOSFETs was performed, aimed at quantifying and comparing the devices’ on-resistance and switching loss. To this end, the relevant material parameters were collected using experimental data where available, or those obtained by simulation. This includes the bulk mobility as a function of doping density, the breakdown field as a function of doping and the MOSFET channel mobility. A device model was constructed and then used to calculate the on-resistance and breakdown voltage of a properly scaled device as a function of the doping density of the blocking layer. A SPICE model was constructed to explore the switching transients and switching losses. The simulations indicate that, for the chosen material parameters, a 600 V 3C-SiC MOSFET has an on-resistance, which is less than half that of a 4H-SiC MOSFET as are the switching losses in the device.

Abstract: High breakdown voltage and smaller size of edge termination are required in SiC power devices. We simulated reverse bias characteristics of a variety of edge terminations targeting 6.5 kV MOSFET and the FLR showed the best trade-off between the size and the implanted Al dose. Fabricated pn diode TEGs with a FLR demonstrated over 6.5 kV breakdown voltage. We observed the avalanche breakdown visually by light emission and it corresponded to the simulated electric field. These indicate that we can fabricate the desirable FLR for 6.5 kV MOSFET.