Materials Science Forum Vol. 924

Abstract: This paper presents the performance, reliability and ruggedness characterization of 1200V, 80mΩ rated SiC planar gate MOSFETs, fabricated in a high volume, 150mm silicon CMOS foundry. The devices showed a specific on-resistance of 5.1 mΩ.cm² at room temperature, increasing to 7.5 mΩ.cm² at 175 °C. Total switching losses were less than 300μJ (V_DD = 800V, I_D = 20A). The devices showed excellent gate oxide reliability with V_TH shifts under 0.2V for extended HTGB stress testing at 175 °C for up to 5500 hours (V_GS = 25V) and 2500 hours (V_GS = -10V). Ruggedness performance such as unclamped inductive load switching and short circuit capability are also discussed.

Abstract: Large-area, 7.84 mm² SiC DMOSFETs feature breakdown voltages of 4600 V, specific on-resistance of 17 mΩ-cm² and gate threshold voltage of 2.4 V. The low on-resistance was enabled by an optimized MOS process that resulted in channel mobility as high as 27 cm²/Vs, and oxide breakdown fields in the 10-11 MV/cm range. The key device design and layout parameters were varied to examine the performance versus reliability trade-offs.

Abstract: The authors have developed 4H-SiC trench MOSFETs with orthogonal Deep-P structures (ODSs) to improve the trade-off between the on-resistance and the gate oxide field. The conditions of photolithography to realize a miniaturized Deep-P pattern have been optimized. The fabricated MOSFETs with ODS have demonstrated a low on-resistance of 2 mΩcm² and a high breakdown voltage of 1.8 kV.

Abstract: Positive bias temperature instability (PBTI) is one of the crucial issues in SiC-MOSFETs’ introduction to automotive applications. We have investigated PBTI of commercially available SiC-MOSFETs under gate-switching operation to consider real power circuits operation. The use of negative gate off-voltage (V_gs(OFF)~-5 V) is shown to suppress V_th shift (ΔV_th) under 100 kHz gate-switching operation. This gate voltage corresponds to the flat band condition, under which the electrons trapped by the near-interfacial traps are effectively detrapped through the interface states around the conduction band edge.

Abstract: An investigation into the robustness of 1200-V/80-mΩ commercial trench-gate MOSFETs reveals that the critical energy for failure during short-circuit operation is reached in shorter times in comparison to similarly rated planar DMOSFETs under similar stress conditions. This critical energy for trench devices was estimated to be between 615 mJ to 660 mJ depending on the gate-drive voltage. These values are considerably smaller when compared to DMOSFETs from the same manufacturer. In comparison to planar designs, trench devices can have lower losses, and manufactured with much smaller chip size for the same device rating. As a result, higher power density, improved efficiency, lower chip costs, and higher yields for trench designs are possible, but these enhancements are offset by a reduction in short-circuit capability. The critical short-circuit time for a 600-V bus voltage is shown to be dependent on gate-drive voltage magnitude, with higher gate voltages leading to increased peak short-circuit current, higher power dissipation, and reduced short-circuit capability.

Abstract: Silicon Carbide (SiC) power MOSFETs become more important in 10kV industrial application level, beginning to replace the silicon devices. Due to the harsh environments, high temperature performances of 10kV SiC MOSFETs must be concerned and understood. In this paper, comprehensive static and dynamic parameters of 10kV SiC MOSFETs have been measured up to 225°C. The device physics behind high temperature behaviors has been analyzed by using the basic analytical models.

Abstract: Standard packages like the TO-247-3L impose a strong restriction on the performance of SiC-transistors. The limitation arises predominantly from the common source inductance L_S that is shared between the gate loop and the load circuit. To avoid this parasitic influence, advanced packages like the TO-247-4L or TO-263-7L offering a Kelvin source connection have been introduced. In this work, the influence of a Kelvin source connection on the switching behavior of a high power SiC-MOSFET is investigated.

Abstract: This work reports an SiC-MOSFET which replaces a part of the channel resistance with an additional embedded resistance, called a source resistance (R_s). MOSFETs with R_s have higher resistance during short circuit compared with MOSFETs without R_s and suppress short-circuit currents. An improvement of the trade-off relationship between short-circuit capability and on-resistance was obtained with MOSFETs including embedded R_s.

Abstract: We fabricated 3300V Silicon Carbide (SiC) DMOSFETs on 150mm substrates in a high volume automotive qualified Si CMOS foundry. In this paper we will show that JFET optimization can yield noticeable improvements in on-state performance without exceeding acceptable gate oxide electric fields. For the optimized design, breakdown voltages (BV) in excess of 3900V are observed along with a specific on resistance of 13.5mOhm-cm² at room temperature and 30mOhm-cm² at 150°C.

Abstract: When power MOSFETs experience a voltage spike initiating avalanche generation, a large amount of power is dissipated at the device junction. This leads to self-heating and lowers the threshold voltage. Some sources indicate that unintended opening of the channel creates a positive feedback, thereby increasing heat generation and leading to thermal runaway. Therefore, keeping MOSFETs off by applying a negative gate bias should improve avalanche ruggedness. In this report, this claim is investigated by comparing single pulse avalanche ruggedness of commercial 1.2 kV, 80 mΩ planar and trench MOSFETs at -10 V and 0 V off-state gate bias. Both planar and trench devices show a small increase in their breakdown voltage with negative gate bias. However, there is no significant difference in avalanche withstanding energy. Even in investigated trench gate devices where the gate oxide is susceptible to interface as well as oxide defects, keeping the gate voltage at V_GS = -10 V did not result in improvements in ruggedness.