Materials Science Forum Vol. 924

Abstract: A correlation between field effect mobility and an accumulation conductance has been investigated at 4H-SiC MOS interface with barium. 4H-SiC n-channel MOSFETs and n-type MOS capacitors were fabricated with a barium-introduced SiO₂ and a conventional dry SiO₂. The field effect mobility was enhanced by introducing the barium-introduced SiO₂. It is found that there is a linear correlation between the mobility and the accumulation conductance. The MOS interface of the barium-introduced SiO₂ had a lower interface state density of 2×10¹¹ cm^-2eV^-1 than that of the conventional dry SiO₂.

Abstract: We investigated the impact of an initial lanthanum oxide (La₂O₃) thickness and forming gas annealing (FGA) conditions on the MOSFET performance. The FGA has been shown to dramatically improve the threshold voltage (V_T) stability of 4H-SiC MOSFETs. The FGA process leads to low V_T shift and high field effect mobility due to reduction of the interface states density as well as traps by passivating the dangling bonds and active traps in the Lanthanum Silicate dielectrics. By optimizing the La₂O₃ interfacial layer thickness and FGA condition, SiC MOSFETs with high threshold voltage and high mobility while maintaining minimal V_T shift are realized.

Abstract: This paper reports on the effect of forming gas annealing on the C-V characteristics and stability of Al2O3/SiC MOS capacitors deposited by atomic layer deposition, (ALD). C-V and I-V measurements were performed to assess the quality of the Al2O3 layer and the Al2O3/SiC interface. In comparison to as-deposited sample, the post oxide annealing (POA) in forming gas at high temperatures has improved the stability of C-V characteristic and the properties at the interface of Al2O3/SiC capacitors. However, the oxide capacitance and oxide breakdown electric field degrade with increased annealing temperature. The results provide indications to improve the performance of Al2O3/SiCcapacitors 4H-SiC devices by optimizing the annealing temperature.

Abstract: 3-Dimensional 4H-SiC metal-oxide-semiconductor capacitors have been fabricated to determine the effect of the sidewall on the characteristics of 3-Dimentional gate structures. Al2O3 deposited by Atomic Layer Deposition (ALD) was used as the gate dielectric layer on the trench structure. The 3-D MOS capacitors exhibit increasing accumulation capacitance with excellent linearity as the sidewall area increases, indicating that ALD results in a highly conformal dielectric film. The capacitance – voltage characteristics also show evidence of a second flatband voltage, located at a higher bias than that seen for purely planar devices on the same sample. We also observe that the oxide capacitance of planar and 3-D MOS capacitors increases with temperature. Finally, we have found that the 3-D MOS capacitor has a weaker temperature dependence of flatband voltage in comparison to the conventional planar MOS capacitor due to the incorporation of the (1120) plane in the sidewall.

Abstract: We report the development of a low-temperature (600 °C) gate oxidation approach to minimize the density of interface traps (D_IT) at the SiC/SiO₂ interface, ultimately leading to a significantly higher channel mobility in SiC MOSFETs of 81 cm²·V^-1·s^-1, >11x higher than devices fabricated alongside but with a conventional 1150 °C gate oxide. We further report on the comparison made between the D_IT and channel mobilities of MOS capacitors and n-MOSFETs fabricated using the low-and high-temperature gate oxidation.

Abstract: This study reports the electrical characteristics and reliability of the atomic layer deposited SiO₂ on the 4H-SiC substrate. By controlling the thickness of SiO₂ in each ALD cycle, improved device properties like mobility and gate leakage were obtained as compared to the single deposition. Moreover, the optimized process dramatically reduces the threshold voltage shift under positive and negative bias stresses. This improvement can be attributed to the effective removal of unreacted metal-organic precursors, active traps, and broken bonds in the ALD SiO₂ dielectrics as well as reduction in interface state density at SiC/SiO₂ interface.

Abstract: In this work, we investigate the effect of borosilicate glass (BSG) as gate dielectric on dielectric/4H-SiC interface traps and channel mobility in 4H-SiC MOSFETs. The interface trap characterization by C−ψs analysis and I-V characterization show lower fast interface trap density (D_it) as well as significant improvement of channel field-effect mobility on devices with BSG than that on devices with standard NO anneal. In addition, the results indicate interface trap density decreases with increasing B concentration at the interface of BSG/4H-SiC, which in turn, results in higher channel mobility.

Abstract: Aluminium oxide was deposited on silicon, silicon carbide and epitaxial graphene grown on silicon carbide by atomic layer deposition using a standard MOCVD equipment. The morphology and the electrical properties of the aluminium oxide layers on both substrates were determined and compared to aluminium oxide layers deposited with a standard atomic layer deposition equipment. The high-k material fabricated with the developed MOCVD process show comparable or better properties compared to the standard atomic layer deposition process.

Abstract: Silicon carbide (SiC) manufacturing is transitioning from 4 inch wafers to 6 inch wafers for production line devices. The main obstacle for SiC manufacturing high yield is defect control. Defectiveness inline control is well established for silicon power device. However, there are two main challenges related to SiC technology. The first challenge is incoming 4H-SiC substrates defectivity and epi layer crystallographic defects. The second challenge is inline defect detection at process steps such as implantation and annealing activation [,]. Defect detection and classification are difficult with current defect inspection tools because of substrate transparency at visible light, color variation, roughness, and wafers’ high warpage. In addition, SiC device integration has been requesting specific optimization. In this paper, collaboration studies have been done to develop solutions to these challenges. Yield correlation analyses have validated the process control flow set to address these two major challenges and to enable the fast ramp of the 6” production line of SiC devices.

Abstract: With the growth in wide bandgap (WBG) semiconductors, specifically Silicon Carbide (SiC), the technology has matured enough to highlight a need to understand the drivers of manufacturing cost, regional manufacturing costs, and plant location decisions. Further, ongoing research and investment, necessitates analytical analysis to help inform development of wide bandgap technologies. The paper explores the anticipated device, module, and motor drive cost at volume manufacturing. It additional outlines the current regional contributors to the supply chain and proposes how the base models can be used to evaluate the cost reduction potential of proposed research advances.