Improved Threshold Voltage Instability in 4H-SiC MOSFETs with Atomic Layer Deposited SiO2

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This study reports the electrical characteristics and reliability of the atomic layer deposited SiO2 on the 4H-SiC substrate. By controlling the thickness of SiO2 in each ALD cycle, improved device properties like mobility and gate leakage were obtained as compared to the single deposition. Moreover, the optimized process dramatically reduces the threshold voltage shift under positive and negative bias stresses. This improvement can be attributed to the effective removal of unreacted metal-organic precursors, active traps, and broken bonds in the ALD SiO2 dielectrics as well as reduction in interface state density at SiC/SiO2 interface.

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Edited by:

Robert Stahlbush, Philip Neudeck, Anup Bhalla, Robert P. Devaty, Michael Dudley and Aivars Lelis

Pages:

498-501

Citation:

M. S. Kang et al., "Improved Threshold Voltage Instability in 4H-SiC MOSFETs with Atomic Layer Deposited SiO2", Materials Science Forum, Vol. 924, pp. 498-501, 2018

Online since:

June 2018

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