Selective Wet Removal of Hf-Based Layers and Post-Dry Etch Residues in High-k and Metal Gate Stacks

Abstract:

• Periodical: Solid State Phenomena (Volumes 103-104)
• Pages: 93-96
• DOI: https://doi.org/10.4028/www.scientific.net/SSP.103-104.93
• Online since: April 2005
• Authors: Martine Claes, Vasile Paraschiv, S. Beckx, M. Demand, W. Deweerd, Sylvain Garaud, H. Kraus, Rita Vos, James Snow, Werner Boullart, Stefan De Gendt
• Keywords: Dry Etch Residue Removal, High-k, Metal Gate, Selective Wet Etching

References

[1] M. Claes et al., The Electrochemical Society Proceedings Series (2003) Physics and Technology of High-K Gate Dielectrics - II (Pennington, NJ, 2003). [2] H. Kraus et al., Selective wet etching of Hf-based layers on a single wafers spin processor, submitted to ISTC Conference, Shangai, China, 2004.

[3] V. Paraschiv et al., to be published in proceedings of this conference (UCPSS 2004).

[4] S. Beckx et al., to be published in proceedings of Workshop on Dielectrics in Microelectronics, WODIM, 28-30 June, Ireland 2004. Figure 1. Different high-k/metal gate stacks under study. Table I. Etch rate of different high-k/metal gate materials in 0.5% HF and aq.-HF/HCl mixture on SEZ tool (SP1200). Figure 2. TEM pictures of resist/polySi/high-k gate (a) before and (b) after non-optimized dry high-k removal (CF4-based chemistry); (c) after partial dry (CF4-based) high-k removal and (d) partial dry followed by selective wet high-k removal ((c) and (d) taken from reference [1]). TiN Hard mask Si or Ge TaN or Ru High-k PolySi mas hardmask TaN or TiN Si b c) PolySi hardmask Si High-k a) -c) d) / resist d) a) Si recess: 1.2 c) b) polySi silicon high-k Recess: 2.5 nm Figure 3. Drive current (nMOS) for dry-only and dry/wet high-k removal approaches. Undercut: 3.8 nm Si recess : ~2 nm Figure 4. TEM result after gate patterning polysilicon/3nm HfSiON/1nm chemical oxide stack with full wet high-k removal. Polymers/ etch residues Figure 5. SEM result after (left) full dry high-k etch with polymerizing BCl3 chemistry and (right) full dry high-k etch with in-situ O2 strip and wet residue removal with HF/acid based solution. poly TaN HK poly TaN HK 2 nm Si recess Figure 6. TEM result of hardmask/polysilicon /PVD TaN/high-k gate with dry high-k removal along with aqueous HF/acid mixture and hardmask removal. 2 0 0 3 0 0 4 0 0 5 0 0 1 0 -1 3 1 0 -1 2 1 0 -1 1 1 0 -1 0 1 0 -9 1 0 -8 1 0 -7 D 0 6 D 0 7 D 0 8 L p o ly = (0 .3 5 - 0 .0 5 ) µm W = 1 µm H K 0 31 6 3 - n M O S Is,off [(VG=0V; VD=1.2V) A/µm] Io n [(V G= V D= 1 .2 V ) µ A /µ m ] NMOS Lpoly = (0.35-0.05) µm W = 1µm Dry only Dry only Dry/wet Etch rate (nm/min) 0.5% HF aqueous- HF/acid Thox 3.2 0.3 PECVD-ox 29.9 3.1 PECVD-ox (plasma treat.) 38 5.2 HDP-ox 5 0.9 TEOS 21.5 2.7 Polysilicon 0.1 0.03 PVD TiN 0.3 0.3 PVD TaN 0.01 0.1 ALD TaN 0.15 0.09 Ru 0 0 HfO2 (as dep) 2.8 1.3 HfO2 (damaged) 4.2 30 HfSiOx(N) on chem. ox. 30 27 HfSiOx(N) on SiON 10 6 Si 0.1 0.16 Ge ~0 ~0