Impact of Galvanic Corrosion on Metal Gate Stacks

Masayuki Wada; Sylvain Garaud; I. Ferain; Nadine Collaert; Kenichi Sano; James Snow; Rita Vos; L.H.A. Leunissens; Paul W. Mertens; Atsuro Eitoku

doi:10.4028/www.scientific.net/SSP.145-146.215

Paper Titles

Influence of Wet Cleaning on Tungsten Deposited with Different Techniques
p.197

Etch Rate Study of Germanium, GaAs and InGaAs: A Challenge in Semiconductor Processing
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Poly-Silicon Etch with Diluted Ammonia: Application to Replacement Gate Integration Scheme
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Advances on 45nm SiGe-Compatible NiPt Salicide Process
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Impact of Galvanic Corrosion on Metal Gate Stacks
p.215

Photoresist Adhesion during Wet Etch on Single Wafer Tool
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Surface Texturization and Interface Passivation of Mono-Crystalline Silicon Substrates by Wet Chemical Treatments
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Mechanism of Plasma-Less Gaseous Etching Process for Damaged Oxides from the Ion Implantation Process
p.227

Current Advances in Anhydrous HF/Organic Solvent Processing of Semiconductor Surfaces
p.231

HomeSolid State PhenomenaSolid State Phenomena Vols. 145-146Impact of Galvanic Corrosion on Metal Gate Stacks

Impact of Galvanic Corrosion on Metal Gate Stacks

Abstract:

High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.