Impact of Galvanic Corrosion on Metal Gate Stacks
High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.
Paul Mertens, Marc Meuris and Marc Heyns
M. Wada et al., "Impact of Galvanic Corrosion on Metal Gate Stacks", Solid State Phenomena, Vols. 145-146, pp. 215-218, 2009