Silicon Surface Passivation in HF Solutions for Improved Gate Oxide Reliability

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Abstract:

The silicon surface passivation with diluted HF solutions is hereby explained. Without a very stable, correct Si-H surface passivation, a rough silicon surface can be obtained, leading to poor gate oxide integrity or bad epi film quality. Detailed mechanism are depicted and solutions to obtain best Si-H passivated surface are given

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Periodical:

Solid State Phenomena (Volume 255)

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8-12

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September 2016

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© 2016 Trans Tech Publications Ltd. All Rights Reserved

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[1] M. Knotter. Etching mechanism of vitreous silicon dioxide in HF-based solutions. J. Am. Chem. Soc., 122 (18), (2000), pp.4345-4351.

DOI: 10.1021/ja993803z

Google Scholar

[2] P. Garnier. Surface preparation challenge on nitrided gate oxides. Solid State phenomena, Vol. 134, (2007) pp.71-74.

DOI: 10.4028/www.scientific.net/ssp.134.71

Google Scholar

[3] Y. Hagimoto, Evaluation of the plasmaless gaseous etching process, Solid State phenomena, Vol. 134, (2008), pp.7-10.

DOI: 10.4028/www.scientific.net/ssp.134.7

Google Scholar

[4] F. Tardiff, optimization of HF and oxidant last wet cleanings before 7nm gate oxide. ECS Fall, (1995), Vol. 95-2.

Google Scholar

[5] Da-Yuan Lee & al. Impacts of HF etching on Ultra-thin core gate oxide integrity in dual gate oxide CMOS technology. Plasma and process-induced damage, (2003), 8th international symposium, pp.77-80.

DOI: 10.1109/ppid.2003.1200921

Google Scholar