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Influences of Cleaning Conditions and Elapse after Etch on Via Resistance in Multi-Level Cu Interconnects

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Ultra Clean Processing of Silicon Surfaces VI

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Periodical:

Solid State Phenomena (Volume 92)

Pages:

259-262

DOI:

https://doi.org/10.4028/www.scientific.net/SSP.92.259

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Online since:

May 2003

Authors:

Uk Sun Hong, Sang Rok Hah, Byung Lyul Park, Chan Geun Park, Jun Hwan Oh, Hong Seong Son, Jeff Barnes, Ju Hyuk Chung, Kwang Myeon Park

Keywords:

Copper (Cu), Elapse, Via Resistance

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© 2003 Trans Tech Publications Ltd. All Rights Reserved

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