Influences of Cleaning Conditions and Elapse after Etch on Via Resistance in Multi-Level Cu Interconnects

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Periodical:

Solid State Phenomena (Volume 92)

Edited by:

Marc Heyns, Paul Mertens and Marc Meuris

Pages:

259-262

DOI:

10.4028/www.scientific.net/SSP.92.259

Citation:

U. S. Hong et al., "Influences of Cleaning Conditions and Elapse after Etch on Via Resistance in Multi-Level Cu Interconnects", Solid State Phenomena, Vol. 92, pp. 259-262, 2003

Online since:

May 2003

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$35.00

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