Papers by Keyword: FET

Abstract: In high current applications that use several parallel-connected SiC MOSFETs (e.g., automotive traction inverters), optimal current sharing is integral to overall system reliability. Threshold voltage (VTH) variation in SiC MOSFETs is a prevalent reliability issue that can cause current mismatch in parallel-connected devices. Using experimental measurements and compact modelling, a technique has been developed for characterising the impact of VTH variation in up to 8 parallel-connected SiC MOSFETs. This model can predict the allowable VTH variation for optimal current sharing. It can also be used to evaluate the impact of other parameters, including gate driver synchronisation, on current sharing in parallel devices.

Abstract: In this paper, we investigated the nitrogen oxides (NO, NO₂) detection capability of strontium titanate (SrTiO₃) when used as sensing layer on gas sensitive silicon carbide field effect transistors (SiC-FETs). Sensitivity, selectivity and response times for NO, NO₂, and NH₃ were characterized, to determine the possibility for diesel exhaust after treatment control applications. It was found that NO_x can be detected down to single digit ppm levels at sensor temperatures in the 550°C - 600°C range. In addition, the results indicate that it is possible to suppress sensitivity to ammonia by selecting an operating temperature around 530°C.

Abstract: In the present work, we report fabrication and electrical characterization of a back gated graphene field effect transistor (GFET). We have focused our study on the interfacial effect (graphene/SiO₂) on the performance of the device. Hysteresis was observed in the drain conductance when measured with respect to dual gate sweep voltage, which increases with increasing sweeping voltage range. The conductance was observed to increase with increase in temperature but there was no reduction in the hysteresis. This proved that temperature annealing could improve the channel conductivity but not the interfacial effects. Further, a metal oxide semiconductor (MOS) device was fabricated with SLG inserted in between the metal and oxide layer and its capacitance-voltage (C-V) characteristics were studied. A small series capacitance (2.1 nF) was observed to be existing in series with the oxide capacitance (4.5 nF) which was attributed to the trap states at the interface of graphene and SiO_2­ layer. Also, the flat band voltage was not affected by the incorporation of graphene layer in the MOS device indicating no change in the work function of the metal gate (Cr/Au). This is an advantageous situation where graphene does not alter its work function also being impermeable, restricts the diffusion of metal particles through the SiO₂.

Abstract: In today's society rapid development of science and technology, the computer figure image design can be widely used in various industries. In the film and television, advertising, exhibition, art, electronic play in areas such as lack of necessary computer graphics design. With the development of computer information technology, the design of the graphics technology will progress. On the technology no longer content with a simple graphics rendering, more note focus on visual sense of the data, enhance the figure shape the image of beauty and expression. This paper mainly discusses the computer graphics design and visual communication design in today's society rapid development of science and technology, computer graphics design has also been extensively applied to various industries. In the film and television, advertising, exhibition, art, video games, and other fields are short of necessary computer graphics design. With the development of information technology, computing machine graphics design technology progress. Current technology is no longer satisfied with the image of a simple now, pay more attention to the visual sensation of biography and enhance the figure shape the image of aesthetic feeling and expression. This paper mainly discusses the computer graphics design and research of visual communication design.

Abstract: Zinc oxide (ZnO) is a one of the most interesting compound semiconductors that received more attention during last few years due to its unique properties. Due to that, this study has been done to manipulate those properties to be used for FET applications. The ZnO thin film has been deposited using the thermal chemical vapor deposition. This is done in a double furnace, which vapored the ZnO powder at different temperature. The growth of the ZnO thin film has been observed using SEM and the electrical properties has been analyzed by using I-V probe station. This is done to study the diode characteristics of ZnO thin film to be used in FET applications.

Abstract: We explore the effect of processing on graphene/metal ohmic contact resistance, the integration of high-κ dielectric seeds and overlayers on carrier transport in epitaxial graphene, and directly demonstrate the importance of buffer elimination at the graphene/SiC(0001) interface for high frequency applications. We present a robust method for forming high quality ohmic contacts to graphene, which improves the contact resistance by nearly 6000x compared to untreated metal/graphene interfaces. Optimal specific contact resistance for treated Ti/Au contacts is found to average -7 Ohm-cm². Additionally, we introduce a novel seeding technique for depositing dielectrics by ALD that utilizes direct deposition of high-κ seed layers and can lead to an increase in Hall mobility up to 70% from as-grown. Finally, we demonstrate that buffer elimination at the graphene/SiC(0001) results in excellent high frequency performance of graphene transistors with f_T > 130 GHz at 75 nm gate lengths.

Abstract: This work discusses the degradations caused by high-energy neutrons in advanced MOSFETs and compares them with damages created by γ-rays reviewing the original researches performed in our laboratory during last years [1-6]. Fully–depleted (FD) Silicon-on-Insulator (SOI) MOSFETs and Multiple-Gate (MuG) FETs with different geometries (notably gate lengths down to 50 nm) have been considered. The impact of radiation on device behavior has been addressed through the variation of threshold voltage (VT), subthreshold slope (S), transconductance maximum (Gmmax) and drain-induced barrier lowering (DIBL). First, it is shown that degradations caused by high-energy neutrons in FD SOI and MuG MOSFETs are largely similar to that caused by γ-rays with similar doses [1,3]. Second, it is revealed that, contrarily to their generally-believed immunity to irradiation [7, 8], very short-channel MuGFETs with thin gate oxide can become extremely sensitive to the total dose effect [2,3]. The possible reason is proposed. Third, a comparative investigation of high-energy neutrons effects on strained and non-strained devices demonstrates a clear difference in their response to high-energy neutrons exposure [6]. Finally, based on simulations and modeling of partially –depleted (PD) SOI CMOS D Flip-Flop, we show how radiation-induced oxide charge and interface states build-up can affect well-known tolerance of SOI devices to transient effects [4,5].

Abstract: Theoretical model of thin film SOI MISFET based on the gate control of impact ionization avalanche in the drain induced p-n+ junction is developed. Such operation principle opens a way of the creation of transistors with high transconductance and operation frequency, and switching between the ON and OFF states by low gate voltage variation.

Abstract: Equivalent sized (4.5 mm2 die area), 1200 V, 4H-SiC, vertical trench Junction Field Effect Transistors (JFETs) were characterized in terms of DC and switching performance. The 100 mΩ Enhancement-Mode (EM) JFET was found to have natural advantages in safe operation being normally-off, whereas the Depletion-Mode (DM) JFET was found to have advantages with ~ twice as high saturation current, less on-resistance (85 mΩ) and no gate current required in the on-state. The JFETs were found to both have radically less (five to ten times) switching energies than corresponding 1200 V Si transistors, with the DM JFET and EM JFET having EON and EOFF of only 115 µJ and 173 µJ, respectively when tested at half-rated voltage (600 V) and 12 A.

Abstract: A gate insulator film with a wide bandgap and a high dielectric constants required to achieve high power field effect transistor (FET) using wide bandgap semiconductors such as SiC and diamond. We can achieve to suppress the gate leakage current and the charge shifts by using the AlSiO film. We found that the leakage current of Nitrogen-doped AlSiO film can be suppressed in high temperature region compared with AlSiO film. In addition, we attempted to study Yttrium aluminate (YAlO) and Lanthanum aluminate (LaAlO) as a gate insulator film. Since the Y (+3) and La(+3) have the same valence as Al (+3), it is expected that there is an advantage that Y, La doping generates less dangling bonds in the Al2O3 film. We can achieve to form aluminum based oxide film with higher dielectric constant by doping Lanthanoid atoms such as Y and La. The optimized YAlO and LaAlO films were applied to SiC-MIS structure. The Lanthanoid and Aluminum based oxide films can readily be applicable to wide bandgap semiconductor devices.