Papers by Keyword: Short-Circuit

Abstract: We present an accurate calibration strategy for TCAD model parameters of a 1200V vertical Silicon-Carbide (SiC) MOSFET, considering key physical characteristics of SiC such as trap distribution along the SiC/SiO₂ interface, mobility degradation, and Schottky contact for the p-type region. Initially, static characteristics are used to calibrate the SiC/SiO₂ interface traps and mobility model parameters in the low electric field region after matching the simulated doping profile with SIMS. Subsequently, capacitance-voltage (C-V) characteristics are calibrated by considering both the capacitance in periphery and the Schottky effect for the p-type well (PWell) region. Finally, the calibrated model was used to evaluate SC withstand time using mixed-mode TCAD simulation. The simulated static and dynamic performance, including short-circuit (SC) withstand time, are in good agreement to the measurements with an error rate of less than 10%. In summary, we propose a TCAD model parameter calibration method for highly accurate simulation of 1200V vertical SiC MOSFETs, which will contribute to finding process and design solutions that consider both static and dynamic characteristics.

Abstract: Silicon Carbide (SiC) is a leading material for power electronics due to its high critical electric field, rapid switching, and high-temperature capabilities. This study delves into the dynamic and thermal performance of a novel SiC power MOSFET, utilizing an innovative vertical Gate All Around (GAA) design. Through detailed 2D TCAD simulations in cylindrical coordinates, the device’s behavior is analyzed across various pillar radii and temperatures. Results indicate that while reducing the pillar radius does not improve the on-resistance (R_ON), a 500 nm radius is required to achieve R_ON < 10 mΩ∙cm². Additionally, larger pillar radii significantly increase capacitance. The device exhibits strong switching performance comparable to commercial counterparts and benefits from the absence of a termination region. However, its short-circuit ruggedness is compromised, particularly in structures with smaller pillar radii, where delayed thermal runaway failure is observed. Notably, for a 20 nm radius, the temperature peak occurs on the Drain side, a deviation from typical behavior. Despite its advantages, the design's low short-circuit capability remains a limitation.

Abstract: Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are successfully replacing traditional silicon insulated gate bipolar transistors (Si IGBTs) in power applications. Nonetheless, two crucial challenges persist: gate-oxide reliability and a reduced short circuit (SC) withstand time. This paper explores a novel MOSFET structure, which is designed to address these concerns and compares it with existing designs through extensive 3D TCAD simulations. The proposed MOSFET structure features a p-region under the gate, providing a unique configuration for improved performance during SC events. This novel structure is then compared to two commercially realized MOSFET structures. Our structure has a superior on-state performance with a specific resistance of 1.48 mΩ /cm², showing an improvement by 25 % and 15 %, respectively. It also increases the blocking capability by 100 V and SC withstand time in comparison to the double-trench MOSFET.

Abstract: Channel density design guidelines for SiC trench-gate MOSFETs with low switching loss, and high short-circuit and avalanche capabilities were proposed. The cell and grounding region pitches were used as parameters to control the channel density to investigate the parameter dependence of each transient property. The results suggest a clear difference in the dependence of switching loss reduction and short-circuit/avalanche capability increase on these parameters; however, the extents of dependence of specific on-resistance on the controlling parameters were comparable. The reduction in the grounding region pitch contributed to faster charging of the parasitic drain-source capacitance, which was effective in improving transient characteristics, such as dV/dt at turn-off, and saturation current at short-circuit. Furthermore, a reduction in this distance increased the area-flowing avalanche current and hence, an increase in the avalanche energy. The influence of the two design parameters in effectively improving the trade-off between each transient characteristic and the specific on-resistance was summarized.

Abstract: Short circuit characteristics of 4H-SiC MOSFETs with different channel lengths are studied in this work. The peak drain-source current during the short-circuit period is measured. These results show that short channel devices has lower capability to sustain short-circuit condition. This work found an evident current tail after the gate turning off. Through the investigation with different device design, circuit condition and numeric simulation. The cause of the current tail is found to be due to the increased ionization of electron-hole pair as the junction temperature is elevated at long short-circuit condition.

Abstract: This work addresses the electrical behaviour of high-voltage (HV) SiC MOSFETs, being the main motivation to check their robustness. Large area (25 mm²) devices rated for 3.3 kV applications were fabricated with a special process for the gate oxide formation. The unit cell was designed to achieve good short-circuit performance. Static and dynamic characterization is presented at room and high temperature. Output curves and 3^rd quadrant behaviour were analysed. Dynamic tests were performed at high bus voltages and high current. To check device robustness, short-circuit and power cycling’s were considered. Robustness test results put in evidence the achievement of reasonable good results obtained due to a suitable cell design.

Abstract: An experimental demonstration of an effective short circuit protection scheme for SiC MOSFETs is presented in this paper. Measurements of the static characteristics of the SiC device before and after the short circuit events were obtained to evince that the device remained in good health. An ultra-fast short circuit protection scheme is implemented given the observed lower short-circuit withstand of present SiC devices. It is shown that the integrity of the SiC device was protected after one-hundred short circuit events.

Abstract: This work investigates the short-circuit capability of SiC cascode by performing two-dimensional electro-thermal TCAD simulations. The effects of the threshold voltage of the SiC JFET on the cascode short-circuit withstand time are studied. A design trade-off between the JFET specific-on resistance and the cascode short-circuit withstand time is determined. The experimental results are also presented.

Abstract: Short-circuit (SC) robustness of 1200 V-rated SiC npn Junction Transistors (SJTs) and commercial power DMOSFETs is investigated. Due to low (2x) overdrive base currents and low short-circuit currents, SJTs demonstrate superior SC capability including: (a) minimum short-circuit withstand time (t_SC) of 14 µs, even at V_DS=1000 V (b) Perfectly stable output and blocking characteristics after 10,000, 10 µs long SC pulses at 800 V, (c) t_SC ≥ 18 µs at 800 V up to (at-least) 175°C base-plate temperatures. In contrast, commercial (Gen-II) 1200 V/80 mΩ SiC MOSFETs exhibit catastrophic failure beyond t_SC = 7 µs at 500 V, and t_SC = 3 µs at 800 V, due to excessive SC currents of > 200 A resulting in junction temperatures in excess of 650°C. The MOSFET’s drain leakage current increases by a factor of 120, and the V_TH reduces by 20%, after 7 µs-long SC pulses at 500 V.

Abstract: With the commercial availability of SiC power transistors, this decade will mark an important breakthrough in power transistor technology. However, in power electronic systems, disturbances may place them in short-circuit condition and little knowledge exist about their SC capability. This paper presents our study of SiC MOSFETs, JFETs and BJT under capacitive load short-circuit up to 600V.