Materials Science Forum Vol. 1092

Abstract: 4H-SiC complementary metal-oxide-semiconductor (CMOS) devices for control circuit applications have been reported extensively, however, the electrical stability, even with interface optimization processes, degrades significantly after bias stress. In this paper, we performed both positive and negative bias stress on planar SiC NMOSFETs and PMOSFETs fabricated with pure (non-diluted) and N₂-diluted NO post-oxidation annealing (POA) processes. The test results indicate the existence of positive hole traps might be the culprit that leads to electrical characteristics instability during operation and pure NO annealing is effective to reduce the instability.

Abstract: Silicon carbide power metal-oxide semiconductor field-effect transistors (MOSFETs) are suitable for more compact and energy efficient electric power conversion, pushing forward numerous key technologies in emission-free mobility and green power generation. These applications require fast gate switching up to hundreds of kilohertz. Typically, to assure a clear turn-off state of the electron channel, a negative turn-off gate bias is used in conjunction with a positive turn-on gate bias. Recently, several reports have revealed a new and so far unknown degradation mechanism that emerges during such operation conditions in apparently all commercial silicon carbide MOSFETs. As this mechanism arises upon gate switching, the terms gate switching instability (GSI) and gate switching stress (GSS) for the mechanism and the associated stress, respectively, have been introduced.Here, we show that this degradation mechanism does not depend on the used frequency up to at least 2 MHz, but that it is actually related to the cumulative number of switching cycles. For this purpose, we performed measurements at various frequencies comprising ultra-fast in-situ measurements of the threshold voltage and pre- and post-stress characterization by impedance analysis. The results are important both for understanding the underlying physics and for developing a correct methodology for industrial device qualification.

Abstract: In this paper the robustness of state of the art SiC MOSFETs is analyzed under repetitivehigh current pulses far beyond the nominal values specified in their data sheets. SiC MOSFETs aremore and more used in many power electronics-based applications, such as industrial motor controlunits. During start-up events or load changes of such motors sudden high current pulses may occur.This imposed stress might trigger the drift of electrical parameters that can limit the operating rangeand lifetime of commercially available SiC MOSFETs. Nevertheless, the tested devices withstoodmillions of repetitive high current pulses several times higher than the rated nominal current withoutany signs of degradation.

Abstract: Power semiconductor modules are subject to both thermo-mechanical stress and electro-chemical stress during field operation. Usually, those stressors are investigated separately and possible interaction of both degradation mechanisms is neglected. In this work, the effect of combined thermo-mechanical and electro-chemical stress is investigated by means of consecutive H3TRB and PCT testing. One test group had been subjected to power cycling before the H3TRB test was performed, while another test group had been exposed to H3TRB stress before the power cycling test. As a reference, devices without preconditioning were tested in both, H3TRB and power cycling and are also used to compare the H3TRB and power cycling performance of the SiC devices to similar silicon devices. The results show, that the SiC devices feature a significantly better H3TRB performance than comparable silicon devices, but are inferior in terms of power cycling performance. Furthermore, the results for both test groups of the combined tests indicate that the failure modes for the previously stressed devices were the same as for the pristine devices and no impact of either preceding stress on the devices' lifetime could be observed. Therefore, the results of this work suggest no interaction between both stressors, at least not for the devices used for this investigation.

Abstract: This study reports on our cutting-edge packaging technology that achieves high power-cycling (PC) durability of silicon carbide (SiC) devices in high-temperature environments up to 250 °C. The key to improving durability is the precise adjustment of the coefficient of thermal expansion (CTE) of the buffer layer bonded onto the SiC chip. It suppresses the creep rupture of the aluminum chip electrode, resulting in a 2.7-fold improvement in the lifetime at 200 °C from the previously reported 334,000 to 905,000 cycles. The developed structure is subjected to a 250 °C test and a lifetime of 350,000 cycles is successfully demonstrated.

Abstract: The avalanche robustness of 430 V SiC avalanche diodes at high temperatures is investigated. The UIS test was performed with fixed avalanche time in order to avoid the effect of a thermal diffusion time on an avalanche energy. It is found that the avalanche energies at 25 are 10.5 J/cm² for and 12.7 J/cm² for while those at 170 are 8.02 J/cm² and 9.96 J/cm², respectively. Their temperature coefficients are about-0.018 J/cm²K, which are much smaller than those of typical SiC-MOSFETs, indicating that the SiC diodes maintain great avalanche robustness even at high temperatures.

Abstract: This work presents very recent results regarding threshold-voltage (V_T) degradation due to the application of an AC gate-bias stress (also known as a gate-switching stress). We show that this phenomenon includes both a seemingly-permanent V_T shift and an increase in the observed V_T hysteresis. This degradation effect is found primarily in trench-geometry devices when exposed to what can be described as a negative bias overstress that exceeds the negative bias rating of the device, but that not all trench devices are equally susceptible, suggesting that device design and processing details are critical in limiting the severity of this effect.

Abstract: The load cycling capability of novel power semiconductors is an important aspect when estimating their lifetime in field service. The Power Cycling Test (PCT) is the standard test to evaluate the lifetime of a semiconductor device under thermo-mechanical stress. PCTs are typically performed at temperature swings (ΔT) much higher than common operating conditions, to obtain results within a reasonable time. In this work, the PCT capability of gallium nitride (GaN) and gallium oxide (Ga2O3) lateral transistors is investigated. The GaN devices were tested in two groups with different ΔT. The temperature of the devices was monitored using two different temperature sensitive electrical parameters (TSEPs) and the accuracy of both methods was evaluated by comparing the results with the temperature, monitored by using an infrared (IR) camera. For Ga2O3 devices, no data on potential TSEP exists so far, thus, the typical TSEP for silicon (Si), silicon carbide (SiC) and GaN were investigated for their applicability to Ga2O3 devices. While a PCT was conducted on the devices, the temperature was also monitored using an IR camera. The results of the comparison of TSEP and IR camera data showed, that the accuracy of the TSEP for GaN matched either the temperature of the hottest spot on the chip (V_DS method), or the average chip temperature (V_GS method). For the Ga2O3 devices no suitable TSEP could be obtained and only the IR camera was used for the temperature measurement. It revealed a very uneven temperature and thus, current distribution on the chip. Furthermore, both GaN and Ga2O3 devices exhibit an outstanding power cycling capability with no failure after completing several millions of cycles. Considering the difference in Young’s Modulus of Si, GaN and Ga2O3, the PCT performance of GaN on silicon devices and Ga2O3 devices should be inferior to silicon devices. Thus, both device types, the GaN transistors and the Ga2O3 transistors, showed a PCT capability much higher than expected.

Abstract: SiC power MOSFETs show very promising electrical performance for efficient and reliable high temperature operation. This work presents a novel approach for the determination of the temperature dependence of SiC power MOSFET’s channel and drift resistance components in the on-state, which are extracted based on current-voltage (I-V) and capacitance-voltage (C-V) measurements without the need of data extrapolation. The results show that the channel resistance has weak, whereas the drift resistance has strong temperature dependence.

Abstract: Silicon carbide (SiC) MOSFETs are gaining more and more market share in typical silicon (Si) IGBT applications such as traction or renewable energies. Especially in reliability sensitive traction applications, medium voltage IGBT-modules (3.3 kV-6.5 kV) are widely used and introducing SiC-MOSFETs to such industries is the next self-evident step already on the way. While their superior electrical performance has been generally accepted already (e.g. [1]), SiC-modules have not yet established a track record of high reliability in this voltage class. For this study, 3.3kV SiC-MOSFET-switches were compared to standard Si-IGBTs regarding their humidity robustness under high voltage bias. Both chip types had been assembled in the same traction rated packages to exclude this influence. The Si-IGBTs resembled the well-known industry standard performance, while the SiC-MOSFETs show no degradation within the reported test time of 2000 h. Given the fact [2], that the latest Si-IGBT generation offers a much better humidity performance as well, the standardised HV-H³TRB is no longer sufficient to provoke failures within a reasonable testing time. On the one hand, this suggests that humidity driven failures will not be an issue under field conditions anymore. On the other hand, even harsher tests are required to investigate differences in humidity performance.