Materials Science Forum Vols. 573-574

Abstract: Millisecond annealing (MSA) has been developed over the last several years as a viable approach to achieve the high electrical activation, limited diffusion and high abruptness needed for junctions in the sub-65nm regime. This paper will provide an overview of the technology including the motivation, technology and some process results. Both main approaches for MSA, sub-melt laser and flash lamp annealing will be discussed as well as the potential challenges to bring these technologies into mainstream manufacturing.

Abstract: In this paper, we investigate the evolution of extended defects during a millisecond Flash anneal after a preamorphising implant. The experimental results, supported by predictive simulations, indicate that during the ultra-fast temperature ramp-up and rump-down occurring in a millisecond Flash anneal, the basic mechanisms that control the growth and evolution of extended defects are not modified with respect to the relatively slower annealing processes, such as “soak” and “spike” Rapid Thermal Annealing. In addition, we have observed a decrease in the number of trapped interstitials in the End-Of-Range (EOR) defects when decreasing the Ge+ amorphisation energy from 30 keV down to 2 keV. This result is ascribed to two concomitant phenomena: (i) the increase of the initial number of interstitials, Ni, created by the amorphisation step, when the implant energy is decreased and (ii) the efficient interstitial annihilation at the silicon surface, whose recombination length, Lsurf, is in the nanometer range even at the very high temperatures employed in millisecond Flash anneals.

Abstract: In this contribution we illustrate some important features of the development of models for the simulation of advanced annealing processes. Taking arsenic as example we discuss the challenges that the last technology trends represent for process modeling. Issues like shallow implants, high doses, low total thermal budgets, and steep temperature profiles are discussed, highlighting the physical phenomena to take into account, and how to design models that reproduce them. We also discuss with examples how important are the critical evaluation of known parameters and established approaches, and the extraction of parameters from experiments. Finally we show some applications of our model for spike and flash annealing of arsenic implants.

Abstract: This paper reviews the physics and the potential application of ion-implanted vacancies for high-performance B-doped ultra-shallow junctions. By treatment of silicon films with vacancygenerating implants prior to boron implantation, electrically active boron concentrations approaching 1021 cm-3 can be achieved by Rapid Thermal Annealing at low temperatures, without the use of preamorphisation. Source/drain (S/D) junctions formed by advanced vacancy engineering implants (VEI) are activated far above solubility. Furthermore, in the case of appropriately engineered thin silicon films, this activation is stable with respect to deactivation and the doping profile is practically diffusionless. Sheet resistance Rs is predicted to stay almost constant with decreasing junction depth Xj, thus potentially outperforming other S/D engineering approaches at the ‘32 nm node’ and beyond.

Abstract: One of the main materials challenges of the 130 nm silicon technology node was the need to find a processing solution to the anomalous diffusion behavior of ion-implanted dopants known from three decades of research. Reduction of implantation energy no longer proved sufficient when trying to reduce source/drain extension junction depth, increase abruptness, and limit sheet resistance. Spike-annealing, a new process in which ion implanted silicon could be heated rapidly to temperatures required for dopant activation and then cooled down without dwelling at temperature, adequately addressed the scaling requirements of this node. The resulting junctions achieved high dopant concentration values very close to the surface while limiting junction depth. However, this increased the propensity for dopant migration to overlying layers associated with the source/drain spacer. Loss of device performance due to this and other phenomena became a strong motivating factor for further materials research in order to sustain progress through the 130 nm and 90 nm nodes. Complex interactions between various layers have been understood and the resulting developments in spacer materials have enabled high performance devices. The requirements of the 65 and 45 nm nodes stretch spike-annealing to its limit and newer ultra-high temperature anneals must be considered.

Abstract: This paper reports on the ultra-rapid thermal annealing of next generation MOSFETs. In ultra-rapid thermal annealing, the most important issue is to achieve a good balance between electrical activation and impurity diffusion. Another issue of annealing implantation damages is also discussed: Optimized annealing combined with millisecond annealing and conventional halogen lamp annealing is necessary for annealing out defects at end-of range region. Application possibilities of millisecond annealing for deep junction activation and oxidation are also discussed.

Abstract: The recent progress of advanced millisecond annealing (MSA) technology is discussed for the application to the advanced logic LSI fabrication processes. The combination with conventional spike annealing and MSA is proving practical to reduce the parasitic resistance and control the dopant diffusion. The characterization result of advanced 45 nm generation devices including the channel straining technology using embedded SiGe epitaxial growth is described with the arrangements of process flow and annealing steps. MSA has a principle problem of the annealing temperature variation depending on the optical properties of materials on the wafer surface because the annealing process time is similar to the heat transfer time. In the device scale, the variation of temperature is examined as the exact temperature with newly proposed evaluating methods used for the first time in this industry.

Abstract: In this paper the formation strategies for source and drain regions in vertical FinFETs are discussed. The technology challenges are very different than for planar bulk devices. Here the main doping approaches are presented with their advantages and drawbacks. Source/drain formation by ion implantation, and deposition techniques are discussed with respect to process simplicity, and device requirements.

Abstract: CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of nMOS (NiSi) and pMOS (Ni-rich) gates on HfSiON is demonstrated. Linewidth independent phase control with smooth threshold voltage (Vt) roll-off characteristics is achieved for NiSi, Ni2Si and Ni31Si12 FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). A 2-step Ni FUSI process enables simultaneous silicidation of nMOS and pMOS FUSI gates, achieving different Ni/Si ratios on nMOS and pMOS by reduction of the pMOS poly height through a selective and controlled poly etch-back prior to gate silicidation. The RTP1 temperature process window to obtain NiSi or Ni3Si2 at the FUSI/dielectric interface (needed for nMOS devices) is significantly widened for spike anneals as compared to soak anneals. Good overlap between the RTP1 process window for nMOS and pMOS devices is achieved by the reduction of the poly-Si height for pMOS.

Abstract: Radiant energy sources enable rapid and controllable thermal processing of wafers with closed-loop control of wafer temperature. However the use of energy sources that are not in thermal equilibrium with the wafers makes the heating process sensitive to the optical properties of the wafers. In particular, patterns on wafer surfaces can cause temperature non-uniformity at length scales where lateral thermal conduction cannot smooth out the effect. Such “pattern effects” are even more significant for advanced processing techniques like millisecond annealing and pulsed laser annealing, because of the extremely large heating powers employed. The issue of pattern effects was recognized early on in the development of radiant heating technology, but has recently become a critical issue for process control. Despite the challenges, many counter-measures can be deployed to minimize pattern effects, including modifications to the wafer design, changes in processing recipe and equipment configuration. Such solutions have enabled the use of radiant heating for even the most demanding device fabrication applications.