Post Metallization Annealing Characterization of Interface Properties of High-κ Dielectrics Stack on Silicon Carbide

Ming Hung Weng; Rajat Mahapatra; Nicolas G. Wright; Alton B. Horsfall

doi:10.4028/www.scientific.net/MSF.600-603.771

Paper Titles

A Study of Deep Energy-Level Traps at the 4H-SiC/SiO₂Interface and Their Passivation by Hydrogen
p.755

Interface and Carrier Transport Behaviour in Al/HfO₂/SiO₂/SiC Structure
p.759

Improved Properties of AlON/4H SiC Interface for Passivation Studies
p.763

Influence of Annealing on the Al₂O₃/4H-SiC Interface
p.767

Post Metallization Annealing Characterization of Interface Properties of High-κ Dielectrics Stack on Silicon Carbide
p.771

Correlation between Thermal Oxide Breakdown and Defects in n-Type 4H-SiC Epitaxial Wafers
p.775

Reliability of Thermal Oxides Grown on n-Type 4H-SiC Implanted with Low Nitrogen Concentration
p.779

Impact of the Wafer Quality on the Reliability of MOS Structure on the C-Face of 4H-SiC
p.783

Gate-Area Dependence of SiC Thermal Oxides Reliability
p.787

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Post Metallization Annealing Characterization of Interface Properties of High-κ Dielectrics Stack on Silicon Carbide

Abstract:

The interface properties of TiO2/SiO2/SiC metal-insulator-semiconductor (MIS) capacitors were investigated by C-V and G-V measurements over a range of frequencies between 10 kHz and 1 MHz from room temperature up to 500°C. Ledges from multiple traps were observed during high frequency (1 MHz) sweeps from inversion to accumulation during measurements at elevated temperatures. The high measuring temperature resulted in the annealing of the sample, where the existence of trap ledges was observed to be temperature dependent. For n-type substrate negative Qf causes the shift of the C-V curve to more negative gate bias with respect to the ideal C-V curve. These fixed oxide charge is substantially reduced after post metallization annealing (PMA). We report the flat band voltage, detail in reducing fixed oxide charge and temperature dependence of density of interface traps before and after annealing of TiO2 high-κ gate dielectric stacks on a 4H-SiC based device.