Post Metallization Annealing Characterization of Interface Properties of High-κ Dielectrics Stack on Silicon Carbide
The interface properties of TiO2/SiO2/SiC metal-insulator-semiconductor (MIS) capacitors were investigated by C-V and G-V measurements over a range of frequencies between 10 kHz and 1 MHz from room temperature up to 500°C. Ledges from multiple traps were observed during high frequency (1 MHz) sweeps from inversion to accumulation during measurements at elevated temperatures. The high measuring temperature resulted in the annealing of the sample, where the existence of trap ledges was observed to be temperature dependent. For n-type substrate negative Qf causes the shift of the C-V curve to more negative gate bias with respect to the ideal C-V curve. These fixed oxide charge is substantially reduced after post metallization annealing (PMA). We report the flat band voltage, detail in reducing fixed oxide charge and temperature dependence of density of interface traps before and after annealing of TiO2 high-κ gate dielectric stacks on a 4H-SiC based device.
Akira Suzuki, Hajime Okumura, Tsunenobu Kimoto, Takashi Fuyuki, Kenji Fukuda and Shin-ichi Nishizawa
M. H. Weng et al., "Post Metallization Annealing Characterization of Interface Properties of High-κ Dielectrics Stack on Silicon Carbide ", Materials Science Forum, Vols. 600-603, pp. 771-774, 2009