Development of Lapping and Polishing Technologies of 4H-SiC Wafers for Power Device Applications
The development of lapping and polishing technologies for SiC single crystal wafers has realized the fabrication of an extremely flat SiC wafer with excellent surface quality. To improve the SiC wafer flatness, we developed a four-step lapping process consisting of four stages of both-side lapping with different grit-size abrasives. We have applied this process to lapping of 2-inch-diameter SiC wafers and obtained an excellent flatness with TTV (total thickness variation) of less than 3 μm, LTV (local thickness variation) of less than 1 μm, and SORI smaller than 10 μm. We also developed a novel MCP (mechano-chemical polishing) process for SiC wafers to obtain a damage-free smooth surface. During MCP, oxidizing agents added to colloidal silica slurry, such as NaOCl and H2O2, effectively oxidize the SiC wafer surface, and then the resulting oxides are removed by colloidal silica. AFM (atomic force microscope) observation of polished wafer surface revealed that this process allows us to have excellent surface smoothness as low as Ra=0.168 nm and RMS=0.2 nm.
Akira Suzuki, Hajime Okumura, Tsunenobu Kimoto, Takashi Fuyuki, Kenji Fukuda and Shin-ichi Nishizawa
H. Yashiro et al., "Development of Lapping and Polishing Technologies of 4H-SiC Wafers for Power Device Applications", Materials Science Forum, Vols. 600-603, pp. 819-822, 2009