Increase of SiC Substrate Resistance Induced by Annealing
We report here an anisotropic increase in SiC bulk resistivity by annealing at 1150 °C, and discuss the implications for SiC devices. The increase in resistivity is resistivity dependent and can be (at least) partially reversed by a subsequent anneal at higher temperature. Ideal device performance is achievable with appropriate annealing steps during device processing.
Anton J. Bauer, Peter Friedrichs, Michael Krieger, Gerhard Pensl, Roland Rupp and Thomas Seyller
T. L. Straubinger et al., "Increase of SiC Substrate Resistance Induced by Annealing", Materials Science Forum, Vols. 645-648, pp. 223-226, 2010