Increase of SiC Substrate Resistance Induced by Annealing

Thomas L. Straubinger; Richard L. Woodin; T. Witt; J. Shovlin; Gary M. Dolny; P. Sasahara; Erwin Schmitt; Arnd Dietrich Weber; Jeff B. Casady; Janna R. B. Casady

doi:10.4028/www.scientific.net/MSF.645-648.223

Paper Titles

Characterization of the Excess Carrier Lifetime of As-Grown and Electron Irradiated Epitaxial p-Type 4H-SiC Layers by the Microwave Photoconductivity Decay Method
p.207

CL/EBIC-SEM Techniques for Evaluation of Impact of Crystallographic Defects on Carrier Lifetime in 4H-SiC Epitaxial Layers
p.211

Nonequilibrium Carrier Recombination in Highly Excited Bulk SiC Crystals
p.215

On the Correlation of the Structural Perfection and Nonequilibrium Carrier Parameters in 3C SiC Heterostructures
p.219

Increase of SiC Substrate Resistance Induced by Annealing
p.223

Barrier Inhomogeneities of Mo Schottky Barrier Diodes on 4H-SiC
p.227

Fundamental Band Edge Absorption in 3C-SiC: Phonon Absorption Assisted Transitions
p.231

Electronic Structure and Momentum-Dependent Resonant Inelastic X-Ray Scattering in Broad Band Materials
p.235

Electronic Properties of Femtosecond Laser Induced Modified Spots on Single Crystal Silicon Carbide
p.239

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Increase of SiC Substrate Resistance Induced by Annealing

Abstract:

We report here an anisotropic increase in SiC bulk resistivity by annealing at 1150 °C, and discuss the implications for SiC devices. The increase in resistivity is resistivity dependent and can be (at least) partially reversed by a subsequent anneal at higher temperature. Ideal device performance is achievable with appropriate annealing steps during device processing.