Materials Science Forum Vols. 778-780

Abstract: The 4H-SiC Schottky barrier diodes for high temperature operation over 200 °C have been developed using buried grids formed by implantation. Compared to a conventional JBS-type SBD with surface grid (SG), JBS-type SBD with buried grid (BG) has significantly reduced leakage current at reverse bias due to a better field shielding of the Schottky contact. By introducing the BG technology, the 1.7 kV diodes with an anode area 0.0024 cm² (1 A) and 0.024 cm² (10 A) were successfully fabricated, encapsulated in TO220 packages, and electrically evaluated. Two types of buried grid arrangement with different grid spacing dimensions were investigated. The measured I-V characteristics were compared with simulation. The best fit was obtained with an active area of approximately 60 % and 70 % of the anode area in large and small devices, respectively. The measured values of the device capacitances were 1000 pF in large devices and 100 pF in small devices at zero bias. The capacitance values are proportional to the device area. The recovery behavior of big devices was measured in a double pulse tester and simulated. The recovery charge, Q_c, was 18 nC and 24 nC in simulation and measurement, respectively. The fabricated BG JBS-type SBDs have a smaller maximum reverse recovery current compared to the commercial devices. No influence of the different grid spacing on the recovery charge was observed.

Abstract: A novel variation of lateral etching junction termination extension (VLE-JTE) for Silicon carbide (SiC) power junction barrier Schottky rectifier (JBS) using a single mask is proposed and investigated. Simulation results shows that the breakdown voltage of JBS terminated with VLE-JTE can achieve 6500V, reaching up to more than 95% of parallel-plane junction bulk breakdown. Moreover, it implements a single mask with window areas varying laterally away from the main junction instead of extra ion implantation or etching steps to achieve multiple-zone JTE, making it easier to be implemented in applications.

Abstract: Based on the theoretical analysis and the simulation results of the ion implantation process and the floating Junction structure, a 4H-SiC SBD with floating junction (FJ_SBD) is fabricated. Compared with the on-resistance 5.13 mΩ·cm² of conventional SBD fabricated at the same time, the on-resistance of FJ_SBD with 3μm P+ buried box is only 6.29 mΩ·cm². The breakdown voltage of the FJ_SBD reaches 950V which is much higher than the 430V of conventional SBD. According to the presented results, The BFOM of the FJ_SBD is 3 times higher than the value of the conventional SBD. It is proved that FJ-SBD has greater prospects for development.

Abstract: This paper presents the temperature and switching rate dependence of 1.2 kV/30 A SiC Schottky diode energy losses in clamped inductive switching circuits with 1.2 kV/30 A SiC MOSFETs as the switching transistors. The devices are tested under an ambient temperature range that spans from -75°C to 175°C and with switching rates that span from 10 to 100 A/μs. Due to the abruptness of the diode turn-OFF, low series resistance and the lack of reverse recovery, SiC SBDs are known to exhibit ringing or electromagnetic oscillations in the presence of parasitic inductances and high switching rates. The impact of these electromagnetic oscillations on the switching energy, the dependence of the switching energy on temperature and the switching rate (dI_DS/dt) is the purpose of this paper’s investigation.

Abstract: One of the attractive methods to reduce the differential resistance of SiC devices is to make the thickness of a SiC substrate thinner [1]. Therefore, we fabricated SiC Schottky barrier diode (SBD) chips with a thickness below 150 μm and the properties of the SiC-SBD chips were measured. It was confirmed that the junction temperature of the thin SiC-SBD chips was decreased by the combination of the reduction in a thickness of the chip and the back side bonding of the chip using a material with high thermal conductivity. Moreover, it was confirmed that the potential of the thin SiC-SBD chip for the surge current capacity could be enhanced to combine the thin SiC-SBD chip with the back side bonding which has high thermal conductivity.

Abstract: This paper presents and compares different avalanche breakdown voltage estimation methods in 4H-SiC (silicon carbide) using finite element simulation results on Schottky diode. 4H-SiC avalanche breakdown voltage and depletion width estimated with Baligas equations have shown to be higher than other estimation techniques and simulation results, especially for voltages higher than 5kV. This paper discusses the impact of choosing different junction termination extension (JTE) structures on two-dimensional junction curvature effects and electric field crowding for Schottky diodes Space-Modulated JTE (SMJTE) structure with optimum JTE dose and dimension could achieve up to 90% of the parallel plane breakdown voltage. For ultra high voltage devices (>15 kV) the SMJTE has significant improvement in terms of breakdown voltage. It also has a wider optimum JTE dose window. For 1 kV device there is not a significant difference in breakdown voltage between JTE and SMJTE structures.

Abstract: We clarified the relationship between the enhanced leakage current of SiC Junction Barrier Schottky diodes and the stacking faults in the SiC crystal at the SiC and metal electrode interface by measuring the electrical and optical properties, and confirm by using the numerical simulations. Numerical simulation considering local lowering of Schottky barrier height, which is 0.8 eV lower than that of 4H-SiC well explained the 2-4 orders of magnitude higher reverse leakage current caused by the SFs. We concluded that the locally lowering of the Schottky barrier height at the 3C-SiC layer in the 4H-SiC surface is a main cause of the large reverse leakage current.

Abstract: Ultrahigh-voltage SiC PiN diodes with an original junction termination extension (JTE) structure and improved forward characteristics are presented. A space-modulated JTE (SM-JTE) structure was designed by device simulation, and a high breakdown voltage of 26.9 kV was achieved by using a 270 μm-thick epilayer and 1050 μm-long JTE. In addition, lifetime enhancement process via thermal oxidation was performed to improve the forward characteristics. The on-resistance of the SiC PiN diodes was remarkably reduced by lifetime enhancement process. The temperature dependence of the on-resistance was also discussed.

Abstract: 10 kV PiN diodes using on-axis 4H-SiC were designed, fabricated, and measured. A lifetime enhancement procedure was done by carbon implantation followed by high temperature annealing to increase lifetime to above 2 μs. The device simulation software Sentaurus TCAD has been used in order to optimize the diode. All fabricated diodes are fully functional and have a V_F of 3.3 V at 100 A/cm² at 25°C, which was decreased to 3.0 V at 300°C.

Abstract: The reverse recovery characteristics of a 4H-SiC PiN diode under higher voltage and faster switching are investigated. In a high-voltage 4H-SiC PiN diode, owing to an increased thickness, the drift region does not become fully depleted at a relatively low voltage Furthermore, an electron–hole recombination must be taken into account when the carrier lifetime is equal to or shorter than the reverse recovery time. High voltage and fast switching are therefore needed for accurate analysis of the reverse recovery characteristics. The current reduction rate increases up to 2 kA/μs because of low stray inductance. The maximum reverse voltage during the reverse recovery time reaches 8 kV, at which point the drift layer is fully depleted. The carrier lifetime at the high level injection is 0.086 μs at room temperature and reaches 0.53 μs at 250 °C.