Materials Science Forum Vols. 778-780

Abstract: SiC lateral MOSFETs with multi-layers epi-channels were studied in this work. The epi-channel with a high concentration n-type epilayer sandwiched by two lightly doped p-type layers showed a maximum field effect mobility of 17 cm²/V.s, improved from 1.53 cm²/V.s of devices without epi-channels. These devices are normally-off with an average threshold voltage of 1.34V.

Abstract: The authors applied a thick gate oxide layer at the trench bottoms to 600 V class truncated V-groove MOSFETs of which MOS channels were formed on 4H-SiC (0-33-8) facets and validated the static and switching characteristics. The specific on-resistance and the threshold voltage were 3.6 mΩ cm² (V_GS=18 V, V_DS=1 V) and about 1 V (normally-off), respectively. The breakdown voltage of the MOSFET with a thick oxide layer was 1,125 V (I_DS=1 μA). The switching losses during turn-on and turn-off operations were estimated to be 105.8 μJ and 82.5 μJ (300 V, 10 A) at room temperature. The switching characteristics exhibited low temperature dependence for turn-on/off time.

Abstract: Silicon carbide double-implanted metal-oxide-semiconductor field-effect transistors (DIMOSFETs) were fabricated on 4H-SiC (000-1) carbon face. The effect of current spread layer (CSL) structure was studied. 1.9 mm × 1.9 mm DIMOSFETs were characterized from room temperature to 200°C. At room temperature, the specific on-resistance of this MOSFET was 14.8 mΩcm² at a gate bias of 20 V and a drain voltage of 0.5 V. The blocking voltage of this MOSFET was 3300 V. At 300 °C, the specific on-resistance increased from 14.8 mΩcm² to 83.9 mΩcm² and the threshold voltage decreased from 5.3 V to 3.4 V.

Abstract: For the first time, a 1200 V 4H-SiC power MOSFET with a monolithically integrated gate buffer circuit has been demonstrated successfully. The device used a 6x10¹⁵ cm^-3 doped, 10 μm thick n-type drift layer to support 1200 V. The gate buffer circuit was built in a p-well, formed by boron ion implantation. The integrated device provided sufficient voltage isolation for the control circuit from the drain of the power MOSFET, and supported internal supply voltages up to 20 V. The operation of the integrated devices was demonstrated. A specific on-resistance (R_on,sp) of 20 mΩ-cm² was observed. The high R_on,sp was due to the limitations in NMOS pull-up circuit topology and the body effect in the 4H-SiC NMOSFET. Development of PMOS pull-up devices is recommended for future integration efforts.

Abstract: Characteristics of high-voltage lateral silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) with various reduced surface field (RESURF) structures were simulated. Breakdown voltage was enhanced from 5300 V for single-zone RESURF to 7400 V for two-zone, and to 7600 V for quasi-modulated RESURF MOSFETs.

Abstract: This work discusses the possibility of using SiC MOSFET body diode in switching power conversion applications, focusing on performance and reliability aspects.

Abstract: In order to achieve cost reduction or shrinkage of power devices, an internal body diode, which forms in a MOSFET parasitically, can be designed as a free-wheeling diode in substitution for an external Schottky barrier diode (SBD). However, in a SiC p-i-n diode, forward current stress causes reliability degradation due to expansion of the electron-hole recombination-induced stacking faults. Applying the process optimization of the epitaxial layer for the reduction of recombination-induced stacking faults and the body diode screening method to 3.3 kV SiC-MOSFETs, we obtained more stable devices under forward current operation.

Abstract: We investigated the SiC-MOSFET with Cu metallization instead of conventional Al metallization to apply to high reliability power modules. As Cu has higher electrical and thermal conductivity, yield strength, and tolerance of its migration than those of Al, applying Cu to metallization and wire bonds will lead to longer lifetime for power modules. One of the major difficulties with Cu metallization is its high diffusivity into SiO₂ and poly-Si which are used as gate oxide, interlayer oxide, and gate electrodes in SiC-MOSFETs, resulting in degradation of devices. We fabricated the SiC-MOSFET with Cu metallization and a diffusion barrier. We have successfully obtained good characteristics same as conventional Al metallization and demonstrated its high temperature reliability.

Abstract: We study the impact of positive bias temperature stress and hot carrier stress on lateral 4H-SiC nMOSFETs. These degradation mechanisms are prominent in silicon based devices where both create oxide as well as interface traps. For SiC MOSFETs only limited information regarding these mechanisms is available. We transfer the charge pumping technique, known from Si MOSFETs, reliably to SiC MOSFETs to learn about the nature of the stress induced defects.

Abstract: The influences of internally unbalanced switching behavior on the switching characteristics and RBSOA were investigated in order to realize a large-size SiC-MOSFET. Specially designed small-size MOSFETs in which the unbalanced behavior is enhanced by adjusting the geometrical gate structures were fabricated, and their switching characteristics were evaluated. It was found that the same switching characteristics can be obtained by regarding them as MOSFETs with high inner gate resistances. A 1-cm² SiC-MOSFET was fabricated, and high dV/dt switching and high turn-off endurance were demonstrated.