Materials Science Forum Vols. 778-780

Abstract: We present new reliability results on the Cree, Inc., 4H-SiC, DMOSFET devices. The Cree DMOSFETs were developed to meet the demand of next-generation, high-frequency power switching applications, such as: dc-ac inversion, dc-dc conversion, and ac-dc rectification, with continually improving energy efficiency. The Cree Generation 2 DMOSFET process technology is now commercially available with 1200 V and 1700 V ratings. We have performed intrinsic reliability studies to ensure excellent wear-out performance and long field lifetime of the products. We have also performed large sample size qualification reliability acceptance tests to ensure the quality of the manufacturing and packaging processes. These comprehensive reliability studies establish new benchmarks for wide bandgap transistors and demonstrate that Crees MOSFETs meet or exceed all industrial reliability requirements. This achievement facilitates broad market adoption of this disruptive power switch technology.

Abstract: In this paper the DC and switching performance of 600V Si, SiC and GaN power devices using device simulation. The devices compared are Si superjunction MOSFET, Si field stop IGBT, SiC UMOSFET and GaN HEMT.

Abstract: 4H-SiC(000-1) C-face was oxidized in H₂O and H₂ mixture gas (H₂ rich wet ambient) for the first time. H₂ rich wet ambient was formed by the catalytic water vapor generator (WVG) system, where the catalytic action instantaneously enhances the reactivity between H₂ and O₂ to produce H₂O. The dependence of SiC oxidation rate on the H₂O partial pressure was investigated. We fabricated 4H-SiC C-face MOS capacitor and MOSFET by the H₂ rich wet re-oxidation following the dry O₂ oxidation. The density of interface traps was reduced and the channel mobility was improved in comparison with the conventional O₂ rich wet oxidation.

Abstract: The Integrated Evaluation Platform for SiC wafers and epitaxial films is established and provide TDDB reliability data such as Q_bd. Accumulated numerous Q_bd data derived from the platform shows three discrete universal distributions (D1>D2>D3) mainly affected by step bunching. On the fairly flat surface, locally spreading step-bunching area formation is caused by the scratches on the CMP surface. The step-bunching area contains large number of step-bunching lines, which correspond to trapezoid-shape defects, stretching in a low along the scratches. Only the downstream bases of the trapezoid-shape defects degrade the Q_bd into D2 from D1 on the flat surface without step bunching.

Abstract: We found that threshold voltage (V_th) of a 4H-SiC MOSFET increases drastically by performing low temperature wet oxidation after nitridation in a gate oxide process. The increment of V_th depends on the wet oxidation conditions. Wet oxidation increases the interface trap density (D_it) at deep level of SiC bandgap and decreases positive charge density inside the gate oxide layer. The amount change of the interface traps and the positive charges in the gate oxide makes V_th higher without a decrease in the channel mobility. We improved the trade-off between V_th and effective carrier mobility (μ_eff) in the MOSFET channel, and realized a low specific on-resistance (R_on,sp) SiC-MOSFET with V_th over 5 V by using the newly developed process.

Abstract: Two kinds of gate oxides, direct thermal oxidation in a nitrous oxide ambient at 1250°C(TGO) and a PECVD oxide followed by a post deposition oxidation in nitrous at 1150°C (DGO) were studied. DGO showed a lower interface trap density and was able to provide a higher current as being implemented in MOSFETs through the improved channel mobility. However the 6.45 MV/cm average breakdown field of DGO is lower than the 10.1 MV/cm breakdown field of TGO. The lower breakdown field, more leaky behavior and the existence of multiple breakdown mechanisms suggest that DGO needs further improvements before it can be used in real applications.

Abstract: MOS interface traps are characterized by device simulation on the basis of temperature dependence of lateral MOS-TEG devices on the same Al-implanted p-type region as vertical device. The simulation shows fairly large D_it in SiO₂/4H-SiC interface, corresponding to the suggested trap density inside the conduction band. Temperature dependence of on-resistance is explained by application of evaluated interface properties to calculation of current voltage properties of vertical DMOSFET.

Abstract: Power MOSFETs based on 4H-SiC have recently been commercialized and so circuit designers require SPICE models for simulation purposes in a range of applications including switch-mode power supplies. We present a selection of SPICE LEVEL 3 parameters and equations that can be used for effective circuit simulation of these MOSFETs, taking into account their unique characteristics for both static and dynamic operation.

Abstract: SiC npn Junction Transistors (SJTs) with current gains as high as 132, low on-resistance of 4 mΩ-cm², and minimal emitter-size effect are demonstrated with blocking voltages > 600 V. 2400 V-class SJTs feature blocking voltages as high as 2700 V combined with on-resistance as low as 5.5 mΩ-cm². A significant improvement in the current gain stability under long-term high current stress is achieved for the SJTs fabricated by the high gain process.

Abstract: Performance of 4H-SiC BJTs fabricated on a single 100mm wafer with different SiC etching and sacrificial oxidation procedures is compared in terms of peak current gain in relation to base intrinsic sheet resistance. The best performance was achieved when device mesas were defined by inductively coupled plasma etching and a dry sacrificial oxide was grown at 1100 °C.