Materials Science Forum Vols. 778-780

Abstract: An analytical model of 4H-SiC metal semiconductor field effect transistor (MESFET) is proposed with buffer layer on high purity semi-insulating (HPSI) 4H-SiC substrate compensated by multiple deep level traps. The contribution of deep level traps (DLT) is projected and verified using two-dimensional simulations (Silvaco^®). The modeled DC characteristics are compared with two-dimensional simulations performed on the same device as considered in the analytical model.The 4H-SiC MESFET is simulated with and without the effect of buffer layer and the electron concentration profiles in different regions are observed from two-dimensional simulations.The electron concentration profiles obtained at channel-substrate interface clearly shows that when the buffer layer is not present, the channel electrons get trapped by the deep level traps used for substrate compensation. It is also observed that the inclusion of buffer layer minimizes the extent of electron trapping by screening out the active channel from the substrate. However, the trapping phenomena take place in both the cases.We believe that the proposed model of 4H-SiC MESFET which includes the substrate compensation through multiple deep level traps may be useful for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

Abstract: This work provides experimental result on fabricated 4H-SiC lateral power MESFET intended to be used in further development of high temperature integrated circuits for power application. The power SiC MESFET device was developed using a planar technology on silicon carbide and P implant isolation technique. Its destination to monolithic integration demands a lateral layout connection topology. The use of quite high doped N type epitaxial layer (10¹⁷cm^-3) typical for the integrated circuits raises difficulties to keep the leakage current of the Schottky gate in a decent range. Therefore, a hexagonal close loop gate in conjunction with three metal interconnection levels was adopted, thus obtaining a compact lateral MESFET device and avoiding any drain to source parasitic leakage path. Using the tungsten gate MESFETS, the first generation of monolithic integrated lateral power MESFET device was integrated on the same wafer with digital circuits and a voltage reference analog circuit able to operate up to 250C. The temperature range can be next improved by using higher barrier for the gate contact.

Abstract: To address safety issue of DC networks in distribution and generation plants, a specific Current Limiting FET has been design. The fabricated power switch is able to operate in both forward and reverse conduction mode. Short-circuit time to failure has been adjust and a current sensing electrode as been added to ease the monitoring and the drive of this switch. Fabricated devices have been packaged in TO3 metal can, providing good heat conduction and durability. A maximum short circuit energy of 70J/cm2 as been measured for a IN = 6 A VBR = 1800 V rated device, corresponding to a short-circuit time before failure of tCC = 21ms under VDC = 300 V .

Abstract: 3 kV normally-off SiC-buried gate static induction transistors (SiC-BGSITs) were fabricated by using an innovative fabrication process that was used by us previously to fabricate 0.7–1.2 kV SiC-BGSITs. The fabricated device shows the lowest specific on-resistance of 9.16 mΩ·cm², compared to all other devices of the same class. The threshold voltage of this device was 1.4 V at room temperature and was maintained at values more than 1 V with normally-off characteristics at 200 °C. The device can block drain voltage of 3 kV with a leakage current density of 6.9 mA/cm².

Abstract: We report a 1700V, 5.5mΩ-cm² 4H-SiC DMOSFET capable of 225°C operation. The specific on-resistance of the DMOSFET designed for 1200V applications is 8.8mΩ-cm² at 225°C, an increase of only 60% compared to the room temperature value. The low specific on-resistance at high temperatures enables a smaller die size for high temperature operation. Under a negative gate bias temperature stress (BTS) at V_GS=-15 V at 225°C for 20 minutes, the devices show a threshold voltage shift of ΔV_TH=-0.25 V demonstrating one of the key device reliability requirements for high temperature operation.

Abstract: A breakdown of a conventional trench SiC-MOSFET is caused by oxide breakdown at the bottom of the trench. We have fabricated a novel trench SiC-MOSFET with buried p+ regions and demonstrated the high breakdown voltage of 1700 V and the specific on-resistance of 3.5 mΩcm².

Abstract: Device technologies of SiC MOSFETs have nearly matured to the level of mass production and one of the remaining tasks is to serve better solutions in view of both costs and performances for practical systems. Elimination of external reverse diodes in inverter circuits is one of the solutions, by which total area of the SiC chips is greatly reduced leading to lower material cost. A DioMOS (Diode in SiC MOSFET) successfully integrates the reverse diode without any increase of the chip size from the original MOS transistor by utilizing an n-type epitaxial channel under the MOS gate for the reverse conduction path of the diode. The basic concept of the DioMOS has been proposed [1]; meanwhile, further reduction of the on-state resistance together with confirmation of high-speed switching is necessary for its application in power switching systems. In this paper, low on-state resistance (Ron) of 40mΩ and blocking voltage (BVds) of 1700V as well as improved switching performances of DioMOS are demonstrated. The measured results suggest DioMOS to be satisfactory for practical use.

Abstract: Blocking characteristics of 2.2 kV and 3.3 kV -class 4H-SiC MOSFETs with various doping conditions for the edge termination region have been investigated. By optimizing the implanted dose into the edge termination structure consisting of junction termination extension (JTE) and field limiting ring (FLR), a breakdown voltage of 3,850 V for 3.3 kV -class MOSFET has been attained. This result corresponds to about 95% of the approximate parallel-plane breakdown voltage estimated from the doping concentration and the thickness of the epitaxial layer. Implanted doping for the JFET region is effective in reducing JFET resistance, resulting in the specific on-resistance of 14.2 mΩcm² for 3.3 kV SiC MOSFETs. Switching characteristics at the high drain voltage of 2.0 kV are also discussed.

Abstract: Ensuring gate oxide reliability and low switching loss is required for a trench gate SiC-MOSFET. We developed a trench gate SiC-MOSFET with a p-type region, named Bottom P-Well (BPW), formed at the bottom of the trench gate for bottom oxide protection. We can see an effective reduction in the maximum bottom oxide electric field (E_ox) and a significant improvement in dynamic characteristics with a grounded BPW, whose dV/dt is 76 % larger than that with a floating BPW due to reduction in gate-drain capacitance (C_gd). The grounded BPW is found to be an effective means of both suppressing E_ox and reducing switching loss.

Abstract: We demonstrate a SiC trench MOSFET with an integrated low Von unipolar heterojunction diode (MOSHJD). A region of the heterojunction diode (HJD) was fabricated in a trench with p⁺-type poly-crystalline silicon on an n^--type epitaxial layer of 4H-SiC. The measured on-resistance (R_on) of the transistor action was 15 mΩcm². The measured V_on of the diode action was 2.2 V at a forward current density of 100 A/cm². The fabrication process of the MOSHJD is simple. First, the trenches of the MOSFET region and the HJD region are formed simultaneously; then poly-crystalline silicon is deposited to form the gate electrode of the MOSFET region and the anode electrode of the HJD region at the same time.