Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 °C to 700 °C

Philip G. Neudeck; David J. Spry; Liang Yu Chen; Dorothy Lukco; Carl W. Chang; Glenn M. Beheim

doi:10.4028/www.scientific.net/MSF.897.567

Paper Titles

Dynamic Characterization of the Threshold Voltage Instability under the Pulsed Gate Bias Stress in 4H-SiC MOSFET
p.549

Comprehensive and Detailed Study on the Modeling of Commercial SiC Power MOSFET Devices Using TCAD
p.553

Cryogenic Characterisation and Modelling of Commercial SiC MOSFETs
p.557

Collector Conductivity Modulation in 1200-V 4H-SiC BJTs (Modeling)
p.563

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 °C to 700 °C
p.567

Improved Switching Characteristics Obtained by Using High-k Dielectric Layers in 4H-SiC IGBT: Physics-Based Simulation
p.571

Simulation Study of Switching-Dependent Device Parameters of High Voltage 4H-SiC GTOs
p.575

Total Dose Effects on 4H-SiC Bipolar Junction Transistors
p.579

16 kV, 75 kHz, 50% Duty Cycle, SiC Photonic Based Bulk Conduction Power Switch Development
p.583

HomeMaterials Science ForumMaterials Science Forum Vol. 897Experimentally Observed Electrical Durability of...

Experimentally Observed Electrical Durability of 4H-SiC JFET ICs Operating from 500 °C to 700 °C

Abstract:

Prolonged 500 °C to 700 °C electrical testing data from 4H-SiC junction field effect transistor (JFET) integrated circuits (ICs) are combined with post-testing microscopic studies in order to gain more comprehensive understanding of the durability limits of the present version of NASA Glenn's extreme temperature microelectronics technology. The results of this study support the hypothesis that T ≥ 500 °C durability-limiting IC failure initiates with thermal stress-related crack formation where dielectric passivation layers overcoat micron-scale vertical features including patterned metal traces.