Materials Science Forum Vol. 954

Abstract: According to the Classical Electrical Theory of Capacitor-to-Resistance Discharge, the Sample of Sic can Be Equivalent to a Parallel Circuit of Resistance and Capacitance. due to the High Resistance of the Wideband-Gap Semiconductors and the Long Discharge Time of the Capacitance, the Samples Resistivity can Be Calculated Manually or by Computer by Applying a Pulse Voltage to the Sample and then Accurately Measuring its Discharge Time. the Measuring Equipment Consists of Sample Stage, Pulse Generator, Charge Converter and Digital Oscilloscope. if High-Speed Data Acquisition Card and Industrial Computer are Used Instead of the Digital Oscilloscope, the Measurement Repeatability can Be Better than 1%, and the Measurement Range is within 10⁴-10¹² Ω•cm.

Abstract: The heating temperature of the silicon carbide sublimation growth crucible is changed by adjusting the output power of the medium frequency induction coil, and the sintering experiments were carried out using NaCl and Al₂O₃ to observe the morphological changes after sintered under different output power, the corresponding temperature was determined, and the corresponding relationship between the output power and the heating temperature was obtained, the precise temperature control was realized. The results of temperature measurement were compared with that of the infrared photoelectric pyrometer. Based on this, the SiC grains were prepared according to the temperature measurement results. The Raman spectroscopy result shows that the SiC polytype was 6H, the SiC grains distributions are homogeneous, and the size of the SiC grains is uniform and dense.

Abstract: In this paper, Ga₂O₃ thin films were grown on c-plane sapphire substrates by metal-organic chemical vapor deposition (MOCVD). There was phase transition for samples grown with different flow rates of triethyl-gallium (TEGa) and deionized water (H₂O). It is found that ε-Ga₂O₃ is difficult to coalesce and the phase mixture by β­Ga₂O₃ takes place if the flow rates of TEGa and H₂O are too high. However, by using multiple-step growth method, the film became fully coalesced. High-quality ε-Ga₂O₃ thin film with atomically flat surface and multilayer morphology was obtained.

Abstract: As SiC power devices are being developed toward ultrahigh-voltage bipolar structures, the density of basal plane dislocations in SiC epilayers has to be minimized. In this work, a special category of basal plane dislocations, i.e. interfacial dislocations, was investigated. Their etch pits were detected at the interface and the microstructure was revealed by cross-section transmission electron microscope analysis.

Abstract: In this work, a 4.5kV/50A 4H-SiC PiN rectifiers with mesa combined with double-JTE structures is successfully developed for high power applications. Two-dimension numerical device simulator Silvaco-TCAD is applied to optimizing the electrical performance of fabricated rectifiers. Mesa-combined double-JTE structure is utilized to achieve a high blocking voltage with a wider optimum process latitude. A forward current is 50 A at room temperature when SiC PiN device bias 4.1 V, while the maximum blocking voltage achieved is 4.7 kV, reaching up to 86% of parallel-plane junction bulk breakdown.

Abstract: SiC MOSFETs are superior candidates as next power semiconductor devices for many power transform systems. Owing to high requirement of stability for the whole application systems, it is essential to explore the optimized structures and operations for SiC MOSFETs with not only the extremely low on resistance but also much higher robustness. Overview on recent device technologies of SiC MOSFETs is given.

Abstract: We reported that high oxidation temperature is attributed to break Si-C bond and release nitrogen gas to nitrogen ions over 1350°C. The capacitance-voltage characteristics of SiO₂/4H-SiC (0001) MOS capacitors fabricated under different thermal oxidation conditions are compared. The dependence of oxidation temperature on device characteristics (such as V_FB and ΔV_FB) is also analyzed. After a high temperature oxidation, the device reliability of SiC MOS is improved. Such behavior can be attributed to the reduction of the interface traps during high temperature oxidation.

Abstract: We fabricated SiO₂/4H-SiC (0001) MOS capacitors with oxidation temperature at 1350°C, followed by post-oxide-annealing (POA) in NO simply by the control of POA temperatures and times. A correlation between the reduction of interface state density and the increasing of N concentration at the interface has been indicated by C-ψ_s measurement and secondary ion mass spectrometry (SIMS). The SiO₂/4H-SiC interface density decreased when POA temperature was elevated, and the sample annealed at 1300°C for 30min showed the lowest interface state density about 1.5×10¹² cm^-2eV^-1 at E_c-E=0.3 eV when the N concentration is 11.5×10²⁰ cm^-3. Meanwhile, the SiO₂ /4H-SiC interface annealed at 1200°C for 120min showed the highest N concentration at the 4H-SiC/SiO₂ interface is 12.5×10²⁰ cm^-3, whereas the interface state density is 2.5×10¹² cm^-2eV^-1 at E_c-E=0.3 eV higher than 1300°C for 30min. The results suggested that higher temperature POA might be much more efficiency in decreased the 4H-SiC MOS interface density with increasing the N area concentration.

Abstract: In this work, we investigated the oxide reliability of 4H-SiC (0001) MOS capacitors, the oxide was fabricated about 60 nm by thermal oxidation temperature at 1350°C, the oxides than annealed at different temperatures and times in diluted NO (10% in N₂). The 4H-SiC MOS structure was analyzed by C-V and I-V measurement. Compared the J-E curves and Weibull distribution curves of charge-to-breakdown for fives samples under different annealing temperature and time, it shows that the high annealing temperature improves the electrical properties as the lifetime enhanced. The mode value of field-to-breakdown (E_BD) for thermal oxides by post-oxide-annealing in NO for 30 min at 1350°C was 10.09 MV/cm, the charge-to-breakdown (Q_BD) of this sample was the highest in all samples, and the Q_BD value at 63.2% cumulative failure rate was 0.15 C/cm². The Q_BD of the sample annealing at 1200°C for 120 min was 0.06 C/ cm². The effects of NO annealing in high temperature enhance the lifetime of electrical properties and field-to-breakdown obviously. It can be demonstrated that the annealing temperature as high as 1300°C for 30 min can be used to accelerate TDDB of SiC MOS gate oxide.

Abstract: 70-um thick homoepitaxial layers with very low defect density were grown on 6-inch 4° off-axis wafers using hot-wall chemical vapor deposition (CVD). Process optimization resulted in reduction of the density of triangular defects from 1.01 cm^-2 to 0.14 cm^-2. The treatment of wafer (CMP or selection) was essential. The in-situ etch process was optimized prior to the epitaxial growth. Junction Barrier Schottky diodes fabricated on the epitaxial films presented a typical I–V characteristic and a block voltage of 6500 V.