Design Optimization of 1.2kV 4H-SiC Trench MOSFET

Tian Xiang Dai; Peter Michael Gammon; Vishal Ajit Shah; Xiao Deng; Michael R. Jennings; Philip  Andrew Mawby

doi:10.4028/www.scientific.net/MSF.963.605

Paper Titles

Achieving Reduced Specific On-Resistance in 1.2 kV SiC Power MOSFETs at Elevated Temperature
p.588

Temperature Dependency of Silicon Carbide MOSFET On-Resistance Characterization and Modeling
p.592

Temperature Dependence of dV/dt Impact on the SiC-MOSFET
p.596

1.2 kV SiC Trench-Gate MOSFETs with Dual Shielding Regions
p.600

Design Optimization of 1.2kV 4H-SiC Trench MOSFET
p.605

Inverse Modeling of 4H-SiC Trench Gate MOSFETs Validated with Electrical and Physical Characterization
p.609

Suppression of Short-Channel Effects in 4H-SiC Trench MOSFETs
p.613

1.2-kV SiC Trench-Etched Double-Diffused MOS (TED-MOS)
p.617

An Investigation into the Dynamic Behavior of 3.3kV MOSFETs Body Diode
p.621

HomeMaterials Science ForumMaterials Science Forum Vol. 963Design Optimization of 1.2kV 4H-SiC Trench MOSFET

Design Optimization of 1.2kV 4H-SiC Trench MOSFET

Abstract:

In a trench MOSFET structure, p+ trench bottom implant (also called p+ shielding region) is commonly used to protect the gate oxide from high electric field stress, however, if the design and fabrication process are not optimized properly, the p+ shielding region together with n-drift and the p-base region will form a parasitic JFET which severely degrades the on-state performance of the device. This paper presents this parasitic JFET effect with experimental results and the optimization work that has been done to eliminate the parasitic JFET.

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Periodical:

Materials Science Forum (Volume 963)

Pages:

605-608

DOI:

https://doi.org/10.4028/www.scientific.net/MSF.963.605

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Online since:

July 2019

Authors:

Tian Xiang Dai*, Peter Michael Gammon, Vishal Ajit Shah, Xiao Deng, Michael R. Jennings, Philip Andrew Mawby

Keywords:

4H-SiC, CSL, Optimization, p⁺ Shielding Region, Parasitic JFET, Trench MOSFET

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References

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