Selective SiGe Etching Formed by Localized Ge Implantation on SOI
The fully depleted SOI devices present lateral isolation issues due to the shallow trench isolation (STI) process. We propose in this paper to study a new fabrication process for integrating local isolation trenches. Germanium (Ge) implantation is used to create SiGe (Silicon-Germanium) layer on thin SOI (silicon on insulator) that can be selectively etched. The advantage is the capability of implantation to localize the SiGe area on this substrate and to avoid STI process issues. Aggressive dimensions and geometries are studied and resulting material transformation (crystallization and Ge diffusion) are apprehending via SEM (Secondary Electron Microscopy) or AFM (Atomic Force Spectroscopy) to understand the etching kinetics. After optimization, we demonstrate the capability of fabricating localized trenches on SOI without degrading the neighboring Si layer or consuming the thin BOX (buried oxide).
B. Pichaud, A. Claverie, D. Alquier, H. Richter and M. Kittler
H. Bourdon et al., "Selective SiGe Etching Formed by Localized Ge Implantation on SOI", Solid State Phenomena, Vols. 108-109, pp. 439-444, 2005