Solid State Phenomena Vol. 359

Abstract: This paper presents results from metal contact processing experiments towards the implementation of durable 500 °C high-frequency 4H-SiC bipolar junction transistors (BJTs). Specifically, p-type ohmic contacts have been demonstrated on a 0.25 μm-thick p-type homoepitaxial layer of doping 8 × 10¹⁸ ± 4 × 10¹⁸ cm^-3. Finally, preliminary current-voltage characteristics of fabricated BJTs are presented.

Abstract: This study examines the impact of supercritical fluid treatment on 1200V 4H-SiC vertical double diffusion MOSFETs (VD-MOSFETs). When exposed to pure carbon dioxide or carbon dioxide mixed with nitrous oxide, there is a significant increase in the improvement ratio of drain current, which is contingent upon channel mobility but has no effect on threshold voltage. Conversely, the degradation of drain current caused by ammonia gas treatment is attributed to a reduction in channel mobility. Furthermore, the treatment with pure carbon dioxide or carbon dioxide mixed with nitrous oxide effectively passivates shallow defects, while the presence of hydrogen atoms in ammonia gas leads to an increase in shallow defects.

Abstract: In this work we have studied hydrogen etching of Silicon Carbide (SiC) chips at high temperatures and in confined limited regions, to elucidate and control the formation and propagation of terraces on the surface of SiC (0001) 4° off-axis samples. This process is very important for the development of high-power transistors. The effects of process parameters on the etching of 4H-SiC (0001) have been extensively investigated using several types of surface analysis (Atomic Force Microscopies (AFM), Scanning Electron Microscope (SEM) and High-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM). We correlated the growth of terraces with etching temperature and time. Moreover, we found the average width of terraces increases decreasing the dimension of the structure from 20 µm to 1 µm using the same process parameters. The nanofacet formation of typical hill-and-valley structure has been observed in localized region on SiC (0001) basal plane.

Abstract: In this study, a novel self-aligned process is proposed to reduce the specific channel resistance, and the electrical characteristics affected by process variation are also verified through TCAD simulation. Also, when compared to other self-aligned processes, the process introduced in this paper offers the advantages of stable electrical characteristics and lower process costs.

Abstract: In this work, we report on the engineering of the SiC/SiO₂ MOS interface using H₂ treatments along with NO POA to improve the interface characteristics and device reliability. Significantly low D_it of 3×10¹¹ eV^-1cm^-2, stable threshold voltage, and long gate oxide lifetime > 10⁵ s have been achieved by H₂ annealing before NO POA of thermal SiO₂. Through device electrical characterization and material analysis, we show that the performance enhancement is due to the reduction of interface defects and trapped charges in the SiO₂ surface layer after the POA treatment, which in turn, significantly suppresses the threshold voltage instability.

Abstract: We present the improvement of SiO₂/4H-SiC interface quality and high field-effect (FE) mobility (µ_FE) in 4H-SiC MOSFETs. This is achieved by introducing a nitrous oxide (N₂O) plasma in-situ pre-treatment before gate stack formation using plasma enhanced chemical vapour deposition (PECVD) oxide followed by a post deposition anneal (PDA) in diluted N₂O for times ranging from 30 to 120 minutes thereby creating an ultra-thin thermally grown SiO₂ layer at the SiO₂/4H-SiC interface. MOS capacitors with SiO₂ deposited on in-situ pre-treated SiC surfaces had a lower density of interface traps (D_IT) for all PDA durations, compared with devices having untreated PECVD oxides or control devices with 30 nm thermally grown oxide. After PDA for 90 minutes, a minimum D_IT value of 1.2×10¹¹ cm^-2·eV^-1 was measured. A peak µ_FE value reaching 94 cm²/(V·s) was measured in n-channel planar MOSFETs fabricated with PECVD oxide on in-situ pre-treated devices, which significantly exceeds a maximum µ_FE of 6 cm²/(V·s) in control devices.

Abstract: Effective control of device geometry is key to mitigating high localized electric fields in next-generation SiC power devices. Advanced trench processing allows for highly tunable trench-gate architectures in trench MOSFETs. By utilizing a two-step inductively coupled plasma reactive ion etch (ICP-RIE) process, a high degree of trench base corner rounding can be achieved, irrespective of trench opening corner geometry prior to post etch treatments. Sentaurus TCAD device modelling highlights the importance of effective electric field dispersion at the gate oxide using rounded trench corners, while I-V characterization of fabricated trench MOS-capacitor devices demonstrate the influence of trench base corner rounding on gate oxide breakdown.

Abstract: This article presents an innovative approach to achieve a high channel mobility for 4H-SiCp-MOSFET via dielectric-semiconductor interface engineering involving atomic layer deposition(ALD) of ultrathin B₂O₃ and SiO₂ stacks. The application of ultrathin boron oxide via ALD introducesa highly manufacturable solution for the passivation of SiC interface. The interface states near valenceband reduces the channel mobility for SiC p-MOSFETs and increases the threshold voltage. Theintroduction of ultrathin B₂O₃ interlayer reduces the threshold voltage and improves the field effectmobility to 12.60 cm²/Vs while the p-MOSFET without the interlayer provides the mobility of 8.91cm²/Vs. This work also includes the optimization of the post-deposition annealing (PDA) conditionsspecific to ultrathin B₂O₃ and bulk SiO₂ dielectric stack to obtain high field effect channel mobilityfor SiO₂/SiC p-MOSFETs.

Abstract: Transition metal ion was added to CMP (chemical-mechanical polishing) slurry without abrasive particle to solve the problem of CMP. MRR (material removal rate) value of SiC substrate processed using non-abrasive slurry was comparable to MRR values of SiC substrates using abrasive slurries. The scratch formation was successfully suppressed in SiC substrate polished with using non-abrasive slurry and no residual particle resulting from agglomeration of abrasive particles could suppress scratches and forms a good quality of SiC substrate surface. Uniform and high-quality SiC substrates could be prepared through the non-abrasive CMP process.

Abstract: The modified SiC slurry for CMP process was proposed in order to obtain high-quality surface of 150 mm SiC wafer and then tried to explain the mechanism of the effect of added transition metal ion to improve polishing characteristics of SiC crystal substrate. SiC substrate with using modified slurry exhibited slightly higher MRR value and lower platen temperature than those with using commercial slurries. The addition of transition metal ion into the slurry enhanced oxidation efficiency of SiC crystal surface and improved MRR and the quality of SiC surface.